Bit Rate Register (Brr1) - Renesas Hitachi H8S/2194 Series Hardware Manual

Bit 1: Multiprocessor Bit (MPB)
When reception is performed using a multiprocessor format in asynchronous mode, MPB stores
the multiprocessor bit in the receive data.
MPB is a read-only bit, and cannot be modified.
Bit 1
MPB Description
0 [Clearing conditions]
When data with a 0 multiprocessor bit is received
1 [Setting conditions]
When data with a 1 multiprocessor bit is received
Note: Retains its previous state when the RE bit in SCR1 is cleared to 0 with multiprocessor
*
format.
Bit 0: Multiprocessor Bit Transfer (MPBT)
When transmission is performed using a multiprocessor format in asynchronous mode, MPBT
stores the multiprocessor bit to be added to the transmit data.
The MPBT bit setting is invalid when a multiprocessor format is not used, when not
transmitting, and in synchronous mode.
Bit 0
MPBT Description
0 Data with a 0 multiprocessor bit is transmitted
1 Data with a 1 multiprocessor bit is transmitted
23.2.8

Bit Rate Register (BRR1)

7
Bit :
1
Initial value :
R/W
R/W :
BRR1 is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate
generator operating clock selected by bits CKS1 and CKS0 in SMR1.
BRR1 can be read or written to by the CPU at all times.
BRR1 is initialized to H'FF by a reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.
Table 23.3 shows sample BRR1 settings in asynchronous mode, and table 23.4 shows sample
BRR1 settings in clock synchronous mode.
6 5
1 1
R/W R/W R/W
4 3 2
1 1 1
R/W R/W
Rev. 2.0, 11/00, page 457 of 1037
(Initial value)*
(Initial value)
1 0
1 1
R/W R/W