Renesas Hitachi H8S/2194 Series Hardware Manual page 817

When the DVTRG bit in the CDVC register is set to 0, reloading is executed with the
switchover timing from PB (ASM) mode to REC mode. To switch from REF30 to
CREF, change the settings of bit 4 (CR/RF bit) in the capstan phase error detection
control register (CPGCR). If synchronization is necessary for phase control, this can be
provided by writing the frequency-division value in CDIVR2.
The down-counters are decremented on rising edges of the CFG signal when the CRF bit
is 0 in the DVCFG control register (CDVC), and on both edges when the CRF bit is 1.
Figure 28.66 shows examples of CFG frequency division waveforms.
CFG
CRF bit=1
CDIVR=00
CRF bit=0
CDIVR=00
CRF bit=0
CDIVR=01
CRF bit=0
CDIVR=02
Rev. 2.0, 11/00, page 790 of 1037
Figure 28.66 Frequency Division Waveforms