Register Configuration - Renesas Hitachi H8S/2194 Series Hardware Manual

17.1.4

Register Configuration

Table 17.2 shows the register configuration of the Timer X1.
Table 17.2 Register Configuration
Name
Timer interrupt enabling register
Timer control/status register X
Free running counter H
Free running counter L
Output comparing register AH
Output comparing register AL
Output comparing register BH
Output comparing register BL
Timer control register X
Timer output comparing control register
Input capture register AH
Input capture register AL
Input capture register BH
Input capture register BL
Input capture register CH
Input capture register CL
Input capture register DH
Input capture register DL
Notes: 1. Only 0 can be written to clear the flag for Bits 7 to 1. Bit 0 is readable/writable.
2. The addresses of the OCRA and OCRB are the same. Changeover between them
are to be made by use of the TOCR bit and OCRS bit.
3. Lower 16 bits of the address.
Rev. 2.0, 11/00, page 358 of 1037
Abbrev. R/W
TIER R/W
TCSRX R/ (W)
FRCH R/W
FRCL R/W
OCRAH R/W
OCRAL R/W
OCRBH R/W
OCRBL R/W
TCRX R/W
TOCR R/W
ICRAH R
ICRAL R
ICRBH R
ICRBL R
ICRCH R
ICRCL R
ICRDH R
ICRDL R
Initial Value
H'00
*1
H'00
H'00
H'00
H'FF
H'FF
H'FF
H'FF
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
*3
Address
H'D100
H'D101
H'D102
H'D103
*2
H'D104
*2
H'D105
*2
H'D104
*2
H'D105
H'D106
H'D107
H'D108
H'D109
H'D10A
H'D10B
H'D10C
H'D10D
H'D10E
H'D10F