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7.7
Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, including NMI input is disabled when flash memory is being programmed or
erased (when the P or E bit is set in FLMCR1), and while the boot program is executing in boot
*1
mode
, to give priority to the program or erase operation. There are three reasons for this:
(1) Interrupt during programming or erasing might cause a violation of the programming or
erasing algorithm, with the result that normal operation could not be assured.
(2) In the interrupt exception handling sequence during programming or erasing, the vector
would not be read correctly
(3) If interrupt occurred during boot program execution, it would not be possible to execute the
normal boot mode sequence.
For these reasons, in on-board programming mode alone there are conditions for disabling
interrupt, as an exception to the general rule. However, this provision does not guarantee normal
erasing and programming or MCU operation. All requests, including NMI input, must therefore
be disabled inside and outside the MCU during FWE application. Interrupt is also disabled in
the error-protection state while the P or E bit remains set in FLMCR1.
Notes: 1. Interrupt requests must be disabled inside and outside the MCU until data write by
the write control program is complete.
2. The vector may not be read correctly in this case for the following two reasons:
• If flash memory is read while being programmed or erased (while the P or E bit is
set in FLMCR1), correct read data will not be obtained (undetermined values will be
returned).
• If the interrupt entry in the interrupt vector table has not been programmed yet,
interrupt exception handling will not be executed correctly.
*2
, possibly resulting in MCU runaway.
Rev. 2.0, 11/00, page 153 of 1037
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