Renesas Hitachi H8S/2194 Series Hardware Manual page 983

H'D0E2: Serial Control Register 2 SCR2: 32-Byte Buffer SCI2
Bit :
7
TEIE
Initial value :
0
R/W : R/W
Transfer interrupt enable bit
0 Transfer interrupt request is disabled
1 Transfer interrupt request is enabled
Transfer end interrupt enable bit
0 Transfer-end interrupt request is disabled
1 Transfer-end interrupt request is enabled
Rev. 2.0, 11/00, page 956 of 1037
6 5 4
—
ABTIE GAP1
0 1 0
—
R/W R/W
Transfer clock select bits
CKS2 CKS1 CKS0 SCK2 pin
0
0
0
0
0
0
0
0
Transfer data interval select bits
GAP1 GAP0 Transfer data interval
0 0 No interval
0 1 8-clock interval
1 0 24-clock interval
0 1 56-clock interval
3 2
GAP0 CKS2
0 0
R/W R/W
Clock source
0 0 SCK2 Sprescaler S
output
0 0
0 0
0 0
0 0
0 0
0 0
0 0 SCK2 External clock
input
1 0
CKS1 CKS0
0 0
R/W R/W
Prescaler frequency Transfer clock frequency
division rate φ = 10 MHz φ = 5 MHz
φ/256 25.6 µs
φ/64 6.4 µs
φ/32 3.2 µs
φ/16 1.6 µs
φ/8 0.8 µs
φ/4 0.4 µs
φ/2 —
— —
51.2 µs
12.8 µs
6.4 µs
3.2 µs
1.6 µs
0.8 µs
0.4 µs
—