Renesas Hitachi H8S/2194 Series Hardware Manual page 509

Figure 23.11 shows an example of SCI1 operation for transmission using a multiprocessor
format.
Start
1
bit
0 D0
TDRE
TEND
Data written to TDR1 and
TXI interrupt
TDRE flag cleared to 0
request
in TXI interrupt handling
general
routine
Figure 23.11 Example of SCI1 Operation in Transmission
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
(b) Multiprocessor Serial Data Reception
Figure 23.12 shows a sample flowchart for multiprocessor serial reception.
The following procedure should be used for multiprocessor serial data reception.
Rev. 2.0, 11/00, page 482 of 1037
Multi-
Data
processor
bit
D1 D7 0/1
TXI interrupt request
generated
1 frame
Data
Stop Start
bit bit
1 0 D0 D1
Multi-
processor
Stop
bit
bit 1
Idle state
D7 0/1 1
(mark state)
TEI interrupt
request
generated