Renesas Hitachi H8S/2194 Series Hardware Manual page 798

Figure 28.56 shows the duty discrimination circuit. A 44% duty cycle is discriminated by
counting with the 16-bit up/down counter, using a φs/4 clock for the up-count and a φs/5 clock
for the down-count. An up-count is performed when the PB-CTL signal is high, and a down-
count when low. Long or short pulse is discriminated by comparing with RCDR2 to RCDR5.
PB-CTL
s/4
s/5
* FWD : Discriminated by RCDR2 and RCDR3
REV : Discriminated by RCDR4 and RCDR5
FWD
REV
* RCDR2or4 (12bit)
* RCDR3or5 (12bit)
s/4
Counter
PB-CTL
1 pulse
s/4
Counter
PB-CTL
0 pulse
RCDR3
Counter
RCDR2
s/4
PB-CTL
Short pulse
(0 pulse)
s/5
RCDR4
Counter
RCDR5
PB-CTL
Long pulse
(1 pulse)
Figure 28.56 Duty Discriminator
UP/DOWN
UP/DOWN counter (16 bits)
Comparison of upper
12-bit
S Q
R
Clear
PB-CTL
s/5
s/5
s/5
s/4
Rev. 2.0, 11/00, page 771 of 1037
UDF
0/1
discrimination
L/S
discrimination
0 pulse L/S threshold value
1 pulse L/S threshold value
0 pulse L/S threshold value
1 pulse L/S threshold value