Renesas Hitachi H8S/2194 Series Hardware Manual page 891

16-bit single-chip microcomputer
Table of Contents

Advertisement

(2) Arithmetic Instructions
Mnemonic
ADD
ADD.B #xx:8,Rd
ADD.B Rs,Rd
ADD.W #xx:16,Rd
ADD.W Rs,Rd
ADD.L #xx:32,ERd
ADD.L ERs,ERd
ADDX
ADDX #xx:8,Rd
ADDX Rs,Rd
ADDS
ADDS #1,ERd
ADDS #2,ERd
ADDS #4,ERd
INC
INC.B Rd
INC.W #1,Rd
INC.W #2,Rd
INC.L #1,ERd
INC.L #2,ERd
DAA
DAA Rd
SUB
SUB.B Rs,Rd
SUB.W #xx:16,Rd
SUB.W Rs,Rd
SUB.L #xx:32,ERd
SUB.L ERs,ERd
SUBX
SUBX #xx:8,Rd
SUBX Rs,Rd
SUBS
SUBS #1,ERd
SUBS #2,ERd
SUBS #4,ERd
DEC
DEC.B Rd
DEC.W #1,Rd
DEC.W #2,Rd
DEC.L #1,ERd
DEC.L #2,ERd
DAS
DAS Rd
MULXU
MULXU.B Rs,Rd
MULXU.W Rs,ERd
MULXS
MULXS.B Rs,Rd
MULXS.W Rs,ERd
DIVXU
DIVXU.B Rs,Rd
DIVXU.W Rs,ERd
DIVXS
DIVXS.B Rs,Rd
DIVXS.W Rs,ERd
CMP
CMP.B #xx:8,Rd
CMP.B Rs,Rd
CMP.W #xx:16,Rd
CMP.W Rs,Rd
CMP.L #xx:32,ERd
CMP.L ERs,ERd
NEG
NEG.B Rd
NEG.W Rd
NEG.L ERd
EXTU
EXTU.W Rd
EXTU.L ERd
EXTS
EXTS.W Rd
EXTS.L ERd
TAS @ERd *
3
TAS
MAC
MAC @ERn+,@ERm+
CLRMAC
CLRMAC
LDMAC
LDMAC ERs,MACH
LDMAC ERs,MACL
STMAC
STMAC MACH,ERd
STMAC MACL,ERd
Rev. 2.0, 11/00, page 864 of 1037
Addressing Mode and Instruction Length (Bytes)
Size
B
2
2
B
W
4
W
2
L
6
L
2
B
2
B
2
L
2
L
2
L
2
B
2
W
2
W
2
L
2
L
2
B
2
B
2
W
4
W
2
L
6
L
2
B
2
B
2
L
2
L
2
L
2
B
2
W
2
W
2
L
2
L
2
B
2
B
2
W
2
B
4
W
4
B
2
W
2
B
4
W
4
B
2
B
2
W
4
W
2
L
6
L
2
B
2
W
2
L
2
W
2
L
2
W
2
L
2
4
B
Cannot be used in this LSI
Operation
Rd8+#xx:8 Rd8
Rd8+Rs8 Rd8
Rd16+#xx:16 Rd16
Rd16+Rs16 Rd16
ERd32+#xx:32 ERd32
ERd32+ERs32 ERd32
Rd8+#xx:8+C Rd8
Rd8+Rs8+C Rd8
ERd32+1 ERd32
ERd32+2 ERd32
ERd32+4 ERd32
Rd8+1 Rd8
Rd16+1 Rd16
Rd16+2 Rd16
ERd32+1 ERd32
ERd32+2 ERd32
Rd8 10 Decimal adjust
Rd8
Rd8-Rs8 Rd8
Rd16-#xx:16 Rd16
Rd16-Rs16 Rd16
ERd32-#xx:32 ERd32
ERd32-ERs32 ERd32
Rd8-#xx:8-C Rd8
Rd8-Rs8-C Rd8
ERd32-1 ERd32
ERd32-2 ERd32
ERd32-4 ERd32
Rd8-1 Rd8
Rd16-1 Rd16
Rd16-2 Rd16
ERd32-1 ERd32
ERd32-2 ERd32
Rd8 10 Decimal adjust
Rd8
Rd8 Rs8 Rd16(Multiplication w/o sign)
Rd16 Rs16 ERd32
(Multiplication w/o sign)
Rd8 Rs8 Rd16(Multiplication w/o sign)
Rd16 Rs16 ERd32
(Multiplication w/o sign)
Rd16 Rs8 Rd16 (RdH: Rmainder, RdL:
Quatient)(Division w/o sign)
ERd32 Rs16 ERd32 (Ed:Remainder,
Rd: Quatient)(Division with sign)
Rd16 Rs8 Rd16(RdH: Rmainder, RdL:
Quatient)(Division w/o sign)
ERd32 Rs16 ERd32 (Ed:Remainder,
Rd: Quatient)(Division with sign)
Rd8-#xx:8
Rd8-Rs8
Rd16-#xx:16
Rd16-Rs16
ERd32-#xx:32
ERd32-ERs32
0-Rd8 Rd8
0-Rd16 Rd16
0-ERd32 ERd32
0 (<Bits 15 to 8> of Rd16)
0 (<Bits 31 to 16> of ERd32)
(<Bit7> of Rd16)
(<Bits 15 to 8> of Rd16)
(<Bit15> of ERd32)
(<Bits31 to 16> of ERd32)
@ERd-0 CCR set, (1)
(<Bit7> of @ERd)
No of
Condition
Execution
Code
States *
1
I
H N Z V C
Advanced Mode
1
1
[3]
2
[3]
1
[4]
3
[4]
1
[5]
1
[5]
1
1
1
1
1
1
1
1
1
*
*
1
1
[3]
2
[3]
1
[4]
3
[4]
1
[5]
1
[5]
1
1
1
1
1
1
1
1
1
*
*
1
12
20
13
21
[6]
[7]
12
[6]
[7]
20
[8]
[7]
13
[8]
[7]
21
1
1
[3]
2
[3]
1
[4]
3
[4]
1
1
1
1
0
0
1
0
0
1
0
1
0
1
0
4
[2]

Advertisement

Table of Contents
loading

Table of Contents