Renesas Hitachi H8S/2194 Series Hardware Manual page 931

Instruction 1
STMAC MACH,ERd Cannot be used in this LSI.
STMAC MACL,ERd
SUB.B Rs,Rd R:W NEXT
SUB.W #xx:16,Rd R:W 2nd
SUB.W Rs,Rd R:W NEXT
SUB.L #xx:32,ERd R:W 2nd
SUB.L ERs,ERd R:W NEXT
SUB #1/2/4,ERd R:W NEXT
SUBX #xx:8,Rd R:W NEXT
SUBX Rs,Rd R:W NEXT
8
TAS @ERd *
R:W 2nd
TRAPA #x:2 R:W NEXT
XOR.B #xx:8,Rd R:W NEXT
XOR.B Rs,Rd R:W NEXT
XOR.W #xx:16,Rd R:W 2nd
XOR.W Rs,Rd R:W NEXT
XOR.L #xx:32,ERd R:W 2nd
XOR.L ERs,ERd R:W 2nd
XORC #xx:8,CCR R:W NEXT
XORC #xx:8,EXR R:W 2nd
Reset exception R:W:M VEC
handling
6
*
Interrupt exception R:W
handling
Notes: 1. EAs is the contents of ER5, and EAd is the contents of ER6.
2. 1 is added to EAs and EAd after execution. n is the initial value of R4L or R4. When
0 is set to n, R4L or R4 is not executed.
3. Repeated twice for 2-unit retract/return, three times for 3-unit retract/return, and four
times for 4-retract/return.
4. Head address after return.
5. Start address of the program.
6. Pre-fetch address obtained by adding 2 to the PC to be retracted.
When returning from sleep mode, standby mode or watch mode, internal operation is
executed instead of read operation.
7. Head address of the interrupt process routine.
8. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Rev. 2.0, 11/00, page 904 of 1037
2 3 4
R:W NEXT
R:W 3nd R:W NEXT
R:W NEXT R:B:M EA W:B EA
Internal W:W stack(L) W:W stack(H) W:W
operation 1
state
R:W NEXT
R:W 3rd R:W NEXT
R:W NEXT
R:W NEXT
R:W VEC+2 Internal R:W
operation 1
state
Internal W:W stack(L) W:W stack(H) W:W
operation 1
state
5 6
R:W:M VEC
stack(EXR)
5
*
R:W:M VEC
stack(EXR)
7 8 9
R:W VEC+2 Internal R:W
operation 1
state
R:W VEC+2 Internal R:W
operation 1
state
7
*
7
*