Renesas Hitachi H8S/2194 Series Hardware Manual page 808

• DVCTL control register (CTVC)
Bit :
7
CEX
Initial value :
0
W
R/W :
Note: * Initial value is uncertain.
The DVCTL control register (CTVC) is a register consisting of the external input signal
selection bit and the flags which show the CFG, HSW and CTL levels.
Note: It has an undetermined value by a reset or stand-by.
Bit 7: DVCTL Signal Generation Selection Bit (CEX)
Selects whether the PB-CTL signal or the external input signal is used to generate the DVCTL
signal.
Bit 7
CEX Description
0 Generates DVCTL signal with PB-CTL signal
1 Generates DVCTL signal with external input signal
Bit 6: External Sync Signal Edge Selection Bit (CEG)
Selects the edge of the external signal at which the frequency division is made when the external
signal was selected to generate the DVCTL signal.
Bit 6
CEG Description
0 Rising edge
1 Falling edge
Bits 5 to 3: Reserved
No write in them is valid. If a read is attempted, an undetermined value is read out.
Bit 2: CFG Flag (CFG)
Shows the CFG level.
Bit 2
CFG Description
0 CFG is at Low level
1 CFG is at High level
6 5
CEG —
0 1
—
W
4 3 2
— — CFG
*
1 1
— —
R
Rev. 2.0, 11/00, page 781 of 1037
1 0
HSW CTL
* *
R R
(Initial value)
(Initial value)
(Initial value)