Renesas Hitachi H8S/2194 Series Hardware Manual page 687

(3) HSW Loop Stage Number Setting Register (HSLP)
Bit :
LOB3
Initial value :
R/W : R/W
Note: * Undetermined
HSLP sets the number of the loop stages when the HSW timing generator is in loop mode. It is
valid if bit 5 (LOP) of HSM2 is 1. Bits 7 to 4 set the number of FIFO2 stages. Bits 3 to 0 set the
number of FIFO1 stages.
HSLP is an 8-bit read/write register. It is not initialized by a reset, stand-by or module stop,
accordingly be sure to set the number of the stages when the loop mode is used.
Rev. 2.0, 11/00, page 660 of 1037
7 6 5
LOB2 LOB1
* * *
R/W R/W
4 3
LOB0 LOA3 LOA2
* *
R/W R/W R/W
2 1 0
LOA1 LOA0
* * *
R/W R/W