Renesas Hitachi H8S/2194 Series Hardware Manual page 714

Bits 7 and 6: Clock Source Selection Bits (DFCS1, DFCS0)
DFCS1 and DFCS0 select the clock to be supplied to the counter. (φs = fosc/2)
Bit 7 Bit 6
DFCS1 DFCS0
0 0
1
1 0
1
Bit 5: Counter Overflow Flag (DFOVF)
The DFOVF flag indicates the overflow of the 16-bit counter. It is cleared by writing 0. Write 0
after reading 1. Also, setting has the highest priority in this flag. If a flag set and 0 write occurs
simultaneously, the latter is nullified.
Bit 5
DFOVF Description
0 Normal state
1 Indicates that overflow has occurred in the counter
Bit 4: Error Data Limit Function Selection Bit (DFRFON)
Makes the error data limit function valid. (Limit values are the values set in the lock range data
register (DFRUDR, DFRLDR)).
Bit 4
DFRFON Description
0 Limit function off
1 Limit function on
Bit 3: Drum Lock Flag (DF-R/UNR)
Sets a flag if an underflow occurred in the drum lock counter.
Bit 3
DF-R/UNR Description
0 Indicates that the drum speed system is not locked
1 Indicates that the drum speed system is locked
Description
φs
φs/2
φs/4
φs/8
(Initial value)
(Initial value)
(Initial value)
(Initial value)
Rev. 2.0, 11/00, page 687 of 1037