Section 27 Address Trap Controller (Atc); Overview; Features; Block Diagram - Renesas Hitachi H8S/2194 Series Hardware Manual

Section 27 Address Trap Controller (ATC)

27.1

Overview

The address trap controller (ATC) is capable of generating interrupt by setting an address to
trap, when the address set appears during bus cycle.
27.1.1

Features

Address to trap can be set independently at three points.
27.1.2

Block Diagram

Figure 27.1 shows a block diagram of the address trap controller.
TRCR
Trap condition comparator
TRCR
TAR0 to 2
Modules bus
TAR0 TAR1
: Trap control register
: Trap address register 0 to 2
Figure 27.1 Block Diagram of ATC
Bus
interface
TAR2
Rev. 2.0, 11/00, page 591 of 1037
Interrupt request