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(5) Noise Detection Window Setting Register (NWR)
7
Bit :
—
Initial value :
1
R/W :
—
NWR sets the period (window) when the drop-out of the pulse of the horizontal sync signal is
detected and the noise is counted. Set the timing of the noise detection window in bits 5 to 0.
Bits 7 and 6 are reserved.
NWR is an 8-bit write-only register. If a read is attempted, an undetermined value is read
out. It is initialized to H'C0 by a reset, stand-by or module stop.
Set the value of the noise detection window timing according to the following equation.
((Value of NWR5 to NWR0) + 1) × 2/φs = 1/4 × TH
Where, TH is the pulse width of the horizontal sync signal (µs), and φs is the servo clock
(fosc/2).
It is recommended that this timing value is set at about 1/4 of the cycle of the horizontal sync
signal.
(6) Noise Detection Register (NDR)
7
Bit :
NDR7
Initial value :
0
R/W :
W
NDR sets the noise detection level when the noise of the horizontal sync signal is detected
(when NWR is set). Set the noise detection level in bits 7 to 0.
NDR is an 8-bit write-only register. No read is valid. If a read is attempted, an
undetermined value is read out. It is initialized to H'00 by a reset, stand-by or module stop.
The noise detector takes counts of the drop-outs of the horizontal sync signals and the noises
within the pulses, and if they amount to a count greater than four times of the value set in
NDR7 to NDR0, the detector sets the NOIS flag in the sync signal control register (SYNCR).
Set the noise detection level at 1/4 of the noise counts in one frame.
The noise counter is cleared whenever Vsync was detected twice.
See section 28.15.6, Noise Detection, for the details of the noise detection window and the
noise detection level.
Rev. 2.0, 11/00, page 802 of 1037
6
5
—
NWR5
NWR4
1
0
W
—
6
5
NDR6
NDR5
NDR4
0
0
W
W
4
3
2
NWR3
NWR2
0
0
0
W
W
W
4
3
2
NDR3
NDR2
0
0
0
W
W
W
1
0
NWR1
NWR0
0
0
W
W
1
0
NDR1
NDR0
0
0
W
W
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