Noise Canceler; Sample Flowcharts - Renesas Hitachi H8S/2194 Series Hardware Manual

25.3.7

Noise Canceler

The logic levels at the SCL and SDA pins are routed through noise cancelers before being
latched internally. Figure 25.13 shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless
the outputs of both latches agree. If they do not agree, the previous value is held.
SCL or SDA
input signal
Sampling
clock
25.3.8

Sample Flowcharts

Figures 25.14 to 25.17 show sample flowcharts for using the I
Rev. 2.0, 11/00, page 560 of 1037
Sampling clock
C
D Q
Latch
System clock
period
Figure 25.13 Block Diagram of Noise Canceler
C
D Q
Latch
2
C bus interface in each mode.
Internal SCL
Match
or SDA signal
detector