Renesas Hitachi H8S/2194 Series Hardware Manual page 812

(2) Register Descriptions
• Register configuration
Table 28.23 shows the register configuration of the CFG frequency divider.
Table 28.23 Register Configuration
Name
DVCFG control register
CFG frequency division
register 1
CFG frequency division
register 2
DVCFG mask period
register
• DVCFG control register (CDVC)
Bit : 7
MCGin
Initial value :
0
R/W *
R/W :
Note: * Only 0 can be written.
CDVC is an 8-bit register to control the capstan frequency division circuit.
It is initialized to H'60 by a reset, stand-by or module stop.
Bit 7: Mask CFG Flag (MCGin)
MCGin is a flag to indicate occurrence of a frequency division signal during the mask timer's
mask period. To clear it, write 0. To clear it by software, write 0 after reading 1. Also, setting
has the highest priority in this flag. If a condition setting the flag and 0 write occurs
simultaneously, the latter is nullified.
Bit 7
MCGin Description
0 CFG is in normal operation
1 Shows that DVCFG was detected during masking (runaway detected)
Bit 6: Reserved
No write in it is valid. If a read is attempted, 1 is read out.
Abbrev. R/W
CDVC R/W
CDIVR1 W
CDIVR2 W
CTMR W
6 5
— CMK CMN
1 1
—
R
Size
Byte
Byte
Byte
Byte
4 3 2
DVTRG CRF
0 0 0
W W W
Rev. 2.0, 11/00, page 785 of 1037
Initial Value Address
H'60 F'FD09A
H'80 H'FD09B
H'80 H'FD09C
H'FF H'FD09D
1 0
CPS1 CPS0
0 0
W W
(Initial value)