Serial Interface Mode Register (Scmr1) - Renesas Hitachi H8S/2194 Series Hardware Manual

23.2.9

Serial Interface Mode Register (SCMR1)

Bit :
7
—
Initial value :
1
R/W :
—
SCMR1 is an 8-bit readable/writable register used to select SCI1 functions.
SCMR1 is initialized to H'F2 by a reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.
Bits 7 to 4: Reserved
These bits cannot be modified and are always read as 1.
Bit 3: Data Transfer Direction (SDIR)
Selects the serial/parallel conversion format.
Bit 3
SDIR Description
0 TDR1 contents are transmitted LSB-first
Receive data is stored in RDR1 LSB-first
1 TDR1 contents are transmitted MSB-first
Receive data is stored in RDR1 MSB-first
Bit 2: Data Invert (SINV)
Specifies inversion of the data logic level. The SINV bit does not affect the logic level of the
parity bit(s): parity bit inversion requires inversion of the O/
Bit 2
SINV Description
0 TDR1 contents are transmitted without modification
Receive data is stored in RDR1 without modification
1 TDR1 contents are inverted before being transmitted
Receive data is stored in RDR1 in inverted form
Rev. 2.0, 11/00, page 464 of 1037
6 5 4
— — —
1 1 1
— — —
3 2
SDIR SINV
0 0
R/W R/W
bit in SMR1.
1 0
— SMIF
1 0
— R/W
(Initial value)
(Initial value)