Table of Contents
Advertisement
H'D106: Timer Control Register X TCRX: Timer X1
7
Bit :
IEDGA
0
Initial value :
R/W :
R/W
Input capture edge select A
0
Capture at falling edge of input capture input A
1
Capture at rising edge of input capture input A
6
5
4
IEDGB
IEDGC
IEDGD
0
0
0
R/W
R/W
R/W
Input capture edge select D
0
1
Input capture edge select C
0
Capture at falling edge of input capture input C
1
Capture at rising edge of input capture input C
Input capture edge select B
0
Capture at falling edge of input capture input B
1
Capture at rising edge of input capture input B
3
2
1
BUFEA
BUFEB
CKS1
0
0
0
R/W
R/W
R/W
Clock selct bit
CKS1
0
0
1
1
Buffer enable B
0
ICRC is not used as buffer register for ICRB
1
ICRC is used as buffer register for ICRB
Buffer enable A
0
ICRC is not used as buffer register for ICRA
1
ICRC is used as buffer register for ICRA
Capture at falling edge of input capture input D
Capture at rising edge of input capture input D
Rev. 2.0, 11/00, page 961 of 1037
0
CKS0
0
R/W
CKS0
Clock select
Internal clock: count at φ/4
0
Internal clock: count at φ/16
1
Internal clock: count at φ/64
0
1
DVCFG: Edge detection p
ulse selected by CFG
frequency division timer
Advertisement
Table of Contents
