Renesas Hitachi H8S/2194 Series Hardware Manual page 856

4.0V
Vcc
OSC1
(Internal)
RES
Note: *
The t
DEXT
Figure 29.3 External Clock Stabilization Delay Timing
t
includes the RES pin Low level width 20 t
RES
V
IL
Figure 29.4 Reset Input Timing
IRQ0 to IRQ5,
V
NMI, IC,
V
ADTRG, TMBI,
FTIA, FTIB,
FTIC, FTID,
TRIG
Figure 29.5 Input Timing
*
DEXT
.
cyc
t
REL
IH
IL
t t
IL IH
Rev. 2.0, 11/00, page 829 of 1037