Renesas Hitachi H8S/2194 Series Hardware Manual page 681

Bit 7: FIFO2 Full Flag (FLB)
When the FLB bit is 1, it indicates that the timing pattern data and the output pattern data of
FIFO2 are full. If a write is attempted in this state, the write operation becomes invalid, an
interrupt is generated, the OVWB flag (bit 3) is set to 1, and the write data is lost. Wait until
space becomes available in the FIFO2, then write again.
Bit 7
FLB Description
0 FIFO2 is not full, and can accept data input
1 FIFO2 is full
Bit 6: FIFO1 Full Flag (FLA)
When the FLA bit is 1, it indicates that the timing pattern data and the output pattern data of
FIFO1 are full. If a write is attempted in this state, the write operation becomes invalid, an
interrupt is generated, the OVWA flag (bit 2) is set to 1, and the write data is lost. Wait until
space becomes available in the FIFO1, then write again.
Bit 6
FLA Description
0 FIFO1 is not full, and can accept data input
1 FIFO1 is full
Bit 5: FIFO2 Empty Flag (EMPB)
Indicates that FIFO2 has no data, or that all the data has been output in single mode.
Bit 5
EMPB Description
0 FIFO2 contains data
1 FIFO2 contains no data
Bit 4: FIFO1 Empty Flag (EMPA)
Indicates that FIFO1 has no data, or that all the data has been output in single mode.
Bit 4
EMPA Description
0 FIFO1 contains data
1 FIFO1 contains no data
Rev. 2.0, 11/00, page 654 of 1037
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