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(2) CFG Speed Error Data Register (CFER)
15
Bit :
Initial value :
0
R/W :
R * /W
R * /W
Note: * Note that only detected error data can be read.
CFER is a 16-bit data register. When the speed of the capstan motor is correct, the data latched
in CFER is H'0000. Negative data will be latched if the speed is too fast, and positive data if the
speed is too slow. The CFER value is sent to the digital filter either automatically or by
software.
CFER is a 16-bit readable/writable register. CFER is accessible by word access only. Byte
access gives unassured results. CFER is initialized to H'0000 by a reset, and in module stop
mode and standby mode.
See the note on the CFG speed preset data register (CFPR) in section 28.8.4 (1).
(3) CFG Lock UPPER Data Register (CFRUDR)
Bit :
15
Initial value :
0
R/W :
W
CFRUDR is a register used to set the lock range on the UPPER side when capstan speed lock is
detected, and to set the limit value on the UPPER side when the limiter function is in use.
When lock is being detected, if the capstan speed is detected within the lock range, the lock
counter which has been set by the CFRCS1 and CFRCS0 bits of the CFVCR register counts
down. If the set value of CFRCS1 and CFRCS0 matches the number of times of occurrence of
locking, the computation of the digital filter in the capstan phase system can be controlled
automatically. Also, if the CFG speed error data is beyond the CFRUDR value when the limiter
function is in use, the CFRUDR value can be used as the data for computation by the digital
filter.
CFRUDR is a 16-bit write-only register. Only a word access is valid. If a byte access is
attempted, operation is not assured. A read is invalid. If a read is attempted, an undetermined
value is read out. It is initialized to H'7FFF by a reset, stand-by or module-stop.
14
13
12
11
10
0
0
0
0
0
R * /W
R * /W
R * /W
R * /W
14
13
12
11
10
1
1
1
1
1
W
W
W
W
W
9
8
7
6
0
0
0
0
R * /W
R * /W
R * /W
R * /W
R * /W R * /W
9
8
7
6
1
1
1
1
W
W
W
W
Rev. 2.0, 11/00, page 705 of 1037
5
4
3
2
1
0
0
0
0
0
R * /W R * /W
R * /W R * /W
5
4
3
2
1
1
1
1
1
1
W
W
W
W
W
0
0
0
1
W
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