Table of Contents
Advertisement
6.4.3
Interrupt Control Mode 1
Three-level masking is implemented for IRQ interrupts and on-chip supporting module
interrupts by means of the I and UI bits in the CPU's CCR, and ICR.
(1) Control level 0 interrupt requests are enabled when the I bit is cleared to 0, and disabled
when set to 1.
(2) Control level 1 interrupt requests are enabled when the I bit or UI bit is cleared to 0, and
disabled when both the I bit and the UI bit are set to 1.
For example, if the interrupt enable bit for an interrupt request is set to 1, and H'04, H'00, H'00
and H'00 are set in ICRA, ICRB, ICRC and ICRD respectively, (i.e. IRQ2 interrupt is set to
control level 1 and other interrupts to control level 0), the situation is as follows:
(1) When I = 0, all interrupts are enabled
(Priority order: NMI > IRQ2 > IC > HSW1 > ...)
(2) When I = 1 and UI = 0, only NMI, address trap and IRQ2 interrupts are enabled
(3) When I = 1 and UI = 1, only NMI and address trap interrupts are enabled
Figure 6.6 shows the state transitions in these cases.
All interrupts enabled
Exception handling
execution or
I
1, UI
Figure 6.6 Example of State Transitions in Interrupt Control Mode 1
Figure 6.7 shows an operation flowchart of interrupt reception.
I
0
1
Only NMI and address trap
interrupts enabled
I
0
Only NMI, address trap and
IRQ2 interrupts enabled
I
1, UI
0
UI
0
Rev. 2.0, 11/00, page 115 of 1037
Exception handling
execution or UI
1
Advertisement
Table of Contents
