Renesas Hitachi H8S/2194 Series Hardware Manual page 224

Store 32-byte program data in program data area
Increment address
Transfer reprogram data to reprogram data area
RAM
Program data storage
area (32 bytes)
Reprogram data
storage area (32 bytes)
1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00, H'20, H'40,
Notes:
H'60, H'80, H'A0, H'C0,, or H'E0. A 32-byte data transfer must be performed even if writing fewer than 32 bytes; in
this case, H'FF data must be written to the extra addresses.
2. Verify data is read in 16-bit (word) units.
3. Even in case of the bit which is already-programmed in the 32-byte programming loop, perform additional
programming if the bit fails at the next verify.
4. An area for storing program data (32 bytes) and reprogram data (32 bytes) must be provided in RAM. The contents
of the latter are rewritten as programming progresses.
5. The values of x, y, z, , , , ,
Program data Verify data
0 0
0 1
1 0
1 1
Figure 8.12 Program/Program-Verify Flowchart
START
Set SWE bit in FLMCR1
Wait (x) µs
*
and reprogram data area
n = 1
m = 0
Write 32-byte data in RAM reprogram data
area consecutively to flash memory
Enable WDT
Set PSU bit in FLMCR1 or FLMCR2
Wait (y) µs *
Set P bit in FLMCR1 or FLMCR2
Start of programming
Wait (z) µs *
Clear P bit in FLMCR1 or FLMCR2
End of programming
Wait ( ) µs
*
Clear PSU bit in FLMCR1 or FLMCR2
Wait ( ) µs
*
Disable WDT
Set PV bit in FLMCR1 or FLMCR2
Wait ( ) µs *
H'FF dummy write to verify address
Wait ( ) µs *
*
Read verify data
NO
Program data = verify data?
YES
Reprogram data computation *
End of 32-byte
data verification?
NO
YES
Clear PV bit in FLMCR1 or FLMCR2
Wait ( ) µs *
NO
m = 0?
YES
Clear SWE bit in FLMCR1
End of
programming
and N are listed in section 29.2.7, Flash Memory Characteristics.
Reprogram data
1 Do not reprogram bits for which
programming has been completed.
0
Programming incomplete; reprogramming
should be performed.
1 —
1 Still in erased state; no action
Programming must be excuted in the erased state.
Do not perform additional programming on
addresses that have already been programmed.
5
4
*
1
*
5
5
5
n n+1
5
5
5
2
m = 1
3
4
*
5
5
*
NO
n N?
YES
Clear SWE bit in FLMCR1
Programming
failure
Comments
Rev. 2.0, 11/00, page 197 of 1037