Page 1 On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding.
Page 2 Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific”...
Page 3 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8S/2158 Group, H8S/2158 F-ZTAT Hardware Manual Renesas 16-Bit Single-Chip Microcomputer...
Page 4 (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp.
Page 5 General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.
Page 6 Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Main Revisions in This Edition The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents.
Page 7 Preface The H8S/2158 is a microcomputer made up of the H8S/2000 CPU employing Renesas Technology’s original architecture as its core, and the peripheral functions required to configure a system, such as a notebook PC and portable information appliance products. The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a simple and optimized instruction set for high-speed operation.
Page 8 URL: http://www.keitaide-music.org/ 3. F-ZTAT™ is a trademark of Renesas Technology Corp. Target Users: This manual was written for users who will be using the H8S/2158 in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers.
Page 9 H8S/2158 manuals: Document Title Document No. H8S/2158 Hardware Manual This manual H8S/2600 Series, H8S/2000 Series Programming Manual REJ09B0139 User’s manuals for development tools: Document Title Document No. H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor REJ10B0058 User’s Manual H8S, H8/300 Series Simulator/Debugger User’s Manual...
Page 10 Rev. 3.00 Jan 25, 2006 page viii of lii...
Page 11 Item Page Revision (See Manual for Details) — All references to Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names changed to Renesas Technology Corp. Designation for categories changed from “series” to “group” Package TQFP (TFP-100B) deleted (Before) TFBGA (TBP-112) → (After) TFBGA (TBP-112A) 5.3.4 IRQ Sense...
Page 12 Item Page Revision (See Manual for Details) 13.3.4 Time Control Table 13.2 amended Register (TCR) TMR_Y when (CKS2, CKS1, CKS0) = (1, 0, 0) (Before) Increments at overflow signal from TCNT_X * → (After) Setting Table 13.2 Clock Input to TCNT and prohibited Count Condition TMR_X when (CKS2, CKS1, CKS0) = (1, 0, 0) (Before)
Page 13 Item Page Revision (See Manual for Details) 16.3.9 Bit Rate Table 16.2 amended Register (BRR) Mode Bit Rate Error Table 16.2 Smart card φ × 10 φ × 10 – 1 × 100 Error (%) = interface mode Relationship between S ×...
Page 14 Item Page Revision (See Manual for Details) 17.3.8 IIC Operation Bit table amended Reservation Adapter ACKXE Status Register A (Before) R/W → (After) R (ICSRA) 17.3.10 IIC Description amended Operation Reservation Bit 0 [Clearing conditions] Adapter Status • When ICDRX is read from with no receive data in the shift Register C (ICSRC) register (SDRF = 0) in receive mode ...
Page 15 Item Page Revision (See Manual for Details) 17.7 Usage Notes 549, Description added 15. Notes on WAIT function (a) Conditions to cause this phenomenon When both of the following conditions are satisfied, the clock pulse of the 9th clock could be outputted continuously in master mode using the WAIT function due to the failure of the WAIT insertion after the 8th clock fall.
Page 16 Item Page Revision (See Manual for Details) 17.7 Usage Notes 550, 16. Notes on Arbitration Lost The I C bus interface recognizes the data in transmit/receive frame as an address when arbitration is lost in master mode and a transition to slave receive mode is automatically carried out.
Page 17: Register Bits
Item Page Revision (See Manual for Details) 17.7 Usage Notes (b) Set the MST bit to 1. (c) To confirm that the bus was not entered to the busy state while the MST bit is being set, check that the BBSY flag in the ICCR register is 0 immediately after the MST bit has been set.
Page 18: Register States
Item Page Revision (See Manual for Details) 28.1 Register Bits Table amended Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module KBCOMP — — — SCANE KBADE KBCH2 KBCH1 KBCH0 converter SCICR IrCKS2...
Page 19: Table Of Contents
Contents Section 1 Overview ......................Features ..........................Internal Block Diagram..................... Pin Description........................1.3.1 Pin Arrangement ....................1.3.2 Pin Arrangement in Each Operating Mode ............1.3.3 Pin Functions ....................... Section 2 CPU ........................17 Features ..........................17 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU ........18 2.1.2 Differences from H8/300 CPU ................
Page 20 2.7.9 Effective Address Calculation................48 Processing States....................... 50 Usage Notes ........................52 2.9.1 Note on TAS Instruction Usage ................52 2.9.2 Note on Bit Manipulation Instructions..............52 2.9.3 EEPMOV Instruction................... 54 Section 3 MCU Operating Modes .................. 55 Operating Mode Selection....................55 Register Descriptions ......................
Page 21 5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR6) Wake-Up Event Interrupt Mask Register (WUEMR3) ........83 Interrupt Sources ....................... 84 5.4.1 External Interrupts ....................84 5.4.2 Internal Interrupts....................86 Interrupt Exception Handling Vector Table..............86 Interrupt Control Modes and Interrupt Operation ............. 90 5.6.1 Interrupt Control Mode 0 ..................
Page 22 6.7.3 Basic Operation Timing ..................138 6.7.4 Wait Control ......................140 Idle Cycle .......................... 141 Bus Arbitration........................142 6.9.1 Bus Master Priority ....................142 6.9.2 Bus Transfer Timing .................... 143 Section 7 Data Transfer Controller (DTC) ..............145 Features ..........................145 Register Descriptions ......................
Page 23 Section 8 RAM-FIFO Unit (RFU) .................. 167 Features ..........................167 Register Descriptions ......................169 8.2.1 FIFO Status/Register/Pointer (FSTR) ..............169 8.2.2 Base Address Register (BAR)................170 8.2.3 Read Address Pointer (RAR) ................170 8.2.4 Write Address Pointer (WAR) ................171 8.2.5 Temporary Pointer (TMP) ...................
Page 24 Section 9 I/O Ports ......................205 Port 1..........................209 9.1.1 Port 1 Data Direction Register (P1DDR)............. 209 9.1.2 Port 1 Data Register (P1DR)................210 9.1.3 Port 1 Pull-Up MOS Control Register (P1PCR)..........210 9.1.4 Pin Functions ....................... 211 9.1.5 Port 1 Input Pull-Up MOS ................... 211 Port 2..........................
Page 25 9.9.1 Port 9 Data Direction Register (P9DDR)............. 250 9.9.2 Port 9 Data Register (P9DR)................251 9.9.3 Pin Functions ....................... 251 9.10 Port A..........................254 9.10.1 Port A Data Direction Register (PADDR) ............254 9.10.2 Port A Output Data Register (PAODR) ............... 254 9.10.3 Port A Input Data Register (PAPIN)..............
Page 26 12.3.2 Output Compare Registers A and B (OCRA and OCRB)........290 12.3.3 Input Capture Registers A to D (ICRA to ICRD) ..........290 12.3.4 Output Compare Registers AR and AF (OCRAR and OCRAF) ......291 12.3.5 Output Compare Register DM (OCRDM) ............291 12.3.6 Timer Interrupt Enable Register (TIER) ..............
Page 27 13.4 Operation........................... 330 13.4.1 Pulse Output......................330 13.5 Operation Timing......................331 13.5.1 TCNT Count Timing.................... 331 13.5.2 Timing of CMFA and CMFB Setting at Compare-Match ........332 13.5.3 Timing of Timer Output at Compare-Match............332 13.5.4 Timing of Counter Clear at Compare-Match ............333 13.5.5 TCNT External Reset Timing ................
Page 28 Section 15 Watchdog Timer (WDT) ................373 15.1 Features ..........................373 15.2 Input/Output Pins ......................375 15.3 Register Descriptions ......................375 15.3.1 Timer Counter (TCNT)..................375 15.3.2 Timer Control/Status Register (TCSR) ..............376 15.4 Operation........................... 379 15.4.1 Watchdog Timer Mode ..................379 15.4.2 Interval Timer Mode ....................
Page 29 16.4.5 SCI Initialization (Asynchronous Mode) ............. 424 16.4.6 Serial Data Transmission (Asynchronous Mode) ..........425 16.4.7 Serial Data Reception (Asynchronous Mode)............427 16.5 Multiprocessor Communication Function................. 431 16.5.1 Multiprocessor Serial Data Transmission ............432 16.5.2 Multiprocessor Serial Data Reception ..............433 16.6 Operation in Clocked Synchronous Mode ................
Page 30 16.11.4 Note on CRC Operation Circuit................472 Section 17 I C Bus Interface (IIC) .................. 473 17.1 Features ..........................473 17.2 Input/Output Pins ......................476 17.3 Register Descriptions ......................476 17.3.1 I C Bus Data Register (ICDR) ................477 17.3.2 Slave Address Register (SAR) ................480 17.3.3 Second Slave Address Register (SARX) .............
Page 31 18.3.1 USB Data FIFO....................557 18.3.2 Endpoint Size Register 1 (EPSZR1) ..............558 18.3.3 Endpoint Data Registers 0S, 0O, 0I, 1, 2, and 3 (EPDR0S, EPDR0O, EPDR0I, EPDR1, EPDR2, and EPDR3)......559 18.3.4 Endpoint Valid Size Registers 0S, 0O, 0I, 1, 2, and 3 (FVSR0S, FVSR0O, FVSR0I, FVSR1, FVSR 2, and FVSR3) ......
Page 32 19.3.2 Command Type Register (CMDTYR)..............632 19.3.3 Response Type Register (RSPTYR) ..............633 19.3.4 Transfer Byte Number Count Register (TBCR) ..........636 19.3.5 Transfer Block Number Counter (TBNCR)............636 19.3.6 Command Registers 0 to 5 (CMDR0 to CMDR5) ..........637 19.3.7 Response Registers 0 to 16, and D (RSPR0 to RSPR16, and RSPRD) ....
Page 33 21.5 Usage Notes ........................695 Section 22 A/D Converter ....................697 22.1 Features ..........................697 22.2 Input/Output Pins ......................699 22.3 Register Descriptions ......................700 22.3.1 A/D Data Registers A to D (ADDRA to ADDRD)..........700 22.3.2 A/D Control/Status Register (ADCSR) ............... 701 22.3.3 A/D Control Register (ADCR) ................
Page 34 24.8.1 Program/Program-Verify ..................733 24.8.2 Erase/Erase-Verify....................735 24.9 Program/Erase Protection....................737 24.9.1 Hardware Protection .................... 737 24.9.2 Software Protection....................737 24.9.3 Error Protection....................737 24.10 Interrupts during Flash Memory Programming/Erasing ........... 738 24.11 Programmer Mode ......................738 24.12 Usage Notes ........................739 Section 25 User Debug Interface (H-UDI) ..............
Page 35 Section 27 Power-Down Modes ..................771 27.1 Register Descriptions ......................772 27.1.1 Standby Control Register (SBYCR) ..............772 27.1.2 Low-Power Control Register (LPWRCR) ............774 27.1.3 System Control Register 2 (SYSCR2) ..............775 27.1.4 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL) Sub-Chip Module Stop Control Registers BH and BL (SUBMSTPBH, SUBMSTPBL) ..
Page 36 Product Lineup........................863 Package Dimensions ......................864 Index ............................865 Rev. 3.00 Jan 25, 2006 page xxxiv of lii...
Page 37 Figures Section 1 Overview Figure 1.1 Internal Block Diagram ..................Figure 1.2 Pin Arrangement (TBP-112A: Top View)............Section 2 CPU Figure 2.1 Exception Vector Table (Normal Mode) .............. 21 Figure 2.2 Stack Structure in Normal Mode ................21 Figure 2.3 Exception Vector Table (Advanced Mode) ............
Page 38 Figure 5.7 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1........................96 Figure 5.8 Interrupt Exception Handling ................97 Figure 5.9 Interrupt Control for DTC..................99 Figure 5.10 Conflict between Interrupt Generation and Disabling .......... 101 Section 6 Bus Controller Figure 6.1 Block Diagram of Bus Controller .................
Page 39 Figure 7.10 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2) .................... 162 Figure 7.11 DTC Operation Timing (Example of Chain Transfer).......... 162 Section 8 RAM-FIFO Unit (RFU) Figure 8.1 Block Diagram of RFU..................168 Figure 8.2 Examples of Temporary Cancellation of Medium-Speed Mode ......
Page 40 Figure 12.9 Buffered Input Capture Timing ................303 Figure 12.10 Buffered Input Capture Timing (BUFEA = 1)............304 Figure 12.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting ....304 Figure 12.12 Timing of Output Compare Flag (OCFA or OCFB) Setting ........ 305 Figure 12.13 Timing of Overflow Flag (OVF) Setting ..............
Page 41 Figure 14.6 2fH Modification Timing Chart................364 Figure 14.7 Fall Modification and IHI Synchronization Timing Chart........366 Figure 14.8 IVG Signal/IHG Signal/CL4 Signal Timing Chart..........369 Figure 14.9 CBLANK Output Waveform Generation ............. 372 Section 15 Watchdog Timer (WDT) Figure 15.1 Block Diagram of WDT ..................
Page 42 Figure 16.18 Sample SCI Initialization Flowchart..............438 Figure 16.19 Sample SCI Transmission Operation in Clocked Synchronous Mode....439 Figure 16.20 Sample Serial Transmission Flowchart..............440 Figure 16.21 Example of SCI Receive Operation in Clocked Synchronous Mode....441 Figure 16.22 Sample Serial Reception Flowchart..............442 Figure 16.23 Sample Flowchart of Simultaneous Serial Transmission and Reception....
Page 43 Figure 17.5 C Bus Formats (Serial Formats)................. 516 Figure 17.6 C Bus Timing ..................... 517 Figure 17.7 Master Transmit Mode Operation Timing Example (MLS = WAIT = 0) .... 519 Figure 17.8 Master Receive Mode Operation Timing Example (1) (MLS = ACKB = 0, WAIT = 1) ................521 Figure 17.9 Master Receive Mode Operation Timing Example (2) (MLS = ACKB = 0, WAIT = 1) ................
Page 44 Figure 18.9 Operation on Receiving an OUT Token (EP5-OUT: Initial FIFO Is Full) ... 613 Figure 18.10 Operation on Receiving an IN Token (EP2-IN: Initial FIFO Is Full) ....614 Figure 18.11 Operation on Receiving an IN Token (EP2-IN: Initial FIFO Is Empty)....615 Figure 18.12 Operation on Receiving an IN Token (EP4-IN: Initial FIFO Is Full) ....
Page 45 Figure 21.2 D/A Converter Operation Example ..............694 Section 22 A/D Converter Figure 22.1 Block Diagram of A/D Converter................. 698 Figure 22.2 A/D Conversion Timing ..................707 Figure 22.3 External Trigger Input Timing................708 Figure 22.4 A/D Conversion Accuracy Definitions ..............710 Figure 22.5 A/D Conversion Accuracy Definitions ..............
Page 46 Figure 26.9 Processing for X1 and X2 Pins ................769 Section 27 Power-Down Modes Figure 27.1 Mode Transition Diagram..................779 Figure 27.2 Medium-Speed Mode Timing................782 Figure 27.3 Software Standby Mode Application Example............. 784 Figure 27.4 Hardware Standby Mode Timing................785 Section 29 Electrical Characteristics Figure 29.1 Darlington Transistor Drive Circuit (Example) ............
Page 47 Appendix Figure C.1 Package Dimensions (TBP-112A) ................. 864 Rev. 3.00 Jan 25, 2006 page xlv of lii...
Page 48 Tables Section 1 Overview Table 1.1 Pin Arrangement in Each Operating Mode ............Table 1.2 Pin Functions......................Section 2 CPU Table 2.1 Instruction Classification..................33 Table 2.2 Operation Notation ....................34 Table 2.3 Data Transfer Instructions ..................35 Table 2.4 Arithmetic Operations Instructions (1)..............
Page 49 Table 5.7 Interrupt Response Times..................98 Table 5.8 Number of States in Interrupt Handling Routine Execution Status......98 Table 5.9 Interrupt Source Selection and Clearing Control............ 100 Section 6 Bus Controller Table 6.1 Pin Configuration ....................105 Table 6.2 Address Ranges and External Address Spaces............115 Table 6.3 Bit Settings and Bus Specifications of Basic Bus Interface ........
Page 50 Table 9.4 Port 3 Input Pull-Up MOS States ................222 Table 9.5 Port 6 Input Pull-Up MOS States ................244 Table 9.6 Port A Input Pull-Up MOS States ................257 Section 10 8-Bit PWM Timer (PWM) Table 10.1 Pin Configuration ....................263 Table 10.2 Internal Clock Selection ..................
Page 51 Table 14.9 Examples of TCR, TCSR, TCORA, TCORB, OCRAR, OCRAF, and TOCR Settings....................368 Table 14.10 HSYNCO Output Modes..................370 Table 14.11 VSYNCO Output Modes..................371 Section 15 Watchdog Timer (WDT) Table 15.1 Pin Configuration ....................375 Table 15.2 WDT Interrupt Source.................... 382 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Table 16.1 Pin Configuration ....................
Page 52 Section 18 Universal Serial Bus Interface (USB) Table 18.1 Pin Configuration ....................555 Table 18.2 FIFO Configuration....................557 Table 18.3 Port 6 Functions ..................... 595 Table 18.4 USB Function Core and Slave CPU Functions ............603 Table 18.5 Packets Included in Each Transaction ..............605 Table 18.6 Registers Initialized by Bit UIFRST or FSRST .............
Page 53 Section 25 User Debug Interface (H-UDI) Table 25.1 Pin Configuration ....................743 Table 25.2 H-UDI Register Serial Transfer................744 Table 25.3 Correspondence between Pins and Boundary Scan Register........747 Section 26 Clock Pulse Generator Table 26.1 Damping Resistance Values ................... 762 Table 26.2 Crystal Resonator Parameters.................
Page 54 Rev. 3.00 Jan 25, 2006 page lii of lii...
Page 55: Section 1 Overview
Section 1 Overview Section 1 Overview Features • High-speed H8S/2000 CPU with an internal 16-bit architecture Upward-compatible with H8/300 CPU and H8/300H CPU on an object level Sixteen 16-bit general registers 65 basic instructions • Various peripheral functions Data transfer controller (DTC) RAM-FIFO unit (RFU) 8-bit PWM timer (PWM) 14-bit PWM timer (PWMX)
Page 56: Internal Block Diagram
Section 1 Overview • Compact package Package Code Body Size Pin Pitch TFBGA-112 TBP-112A 10.0 × 10.0 mm 0.8 mm Internal Block Diagram XTAL EXTAL PA0/A16/KIN8/SSE0I PA1/A17/KIN9/SSE2I RESO STBY P10/A0/PW0/CPA0 H8S/2000 CPU P11/A1/PW1/CPA1 ETRST P12/A2/PW2/CPA2 ETMS P13/A3/PW3/CPA3 ETDO P14/A4/PW4/CPA4 ETDI P15/A5/PW5/CPA5 ETCK Interrupt...
Page 57: Pin Description
Section 1 Overview Pin Description 1.3.1 Pin Arrangement 1 2 3 4 5 6 7 8 9 1011 TBP-112A (Top View) Pin Name Pin Name Pin Name P57/IRQ15/PWX1 (Reserved) P92/CPCS1 P90/LWR P83/ExIRQ11/SDA1 STBY ETCK P80/ExIRQ8/SCL0 P67/D7/CPD7/CIN7/KIN7/DPLS P84/ExIRQ12/SCK0/ExTMI0 AVCC/DrVCC P36/D14/CPD14/WUE14 P75/ExIRQ5/AN5 P33/D11/CPD11/WUE11/MCDATDIR/MCCSA PA1/A17/KIN9/SSE2I P30/D8/CPD8/WUE8/MCCLK...
Page 58: Pin Arrangement In Each Operating Mode
Section 1 Overview 1.3.2 Pin Arrangement in Each Operating Mode Table 1.1 Pin Arrangement in Each Operating Mode Pin No. Pin Name Extended Mode Single-Chip Mode Flash Memory Modes 2 and 3 Modes 2 and 3 Programmer TBP-112A (EXPE = 1) (EXPE = 0) Mode XTAL...
Page 59 Section 1 Overview Pin No. Pin Name Extended Mode Single-Chip Mode Flash Memory Modes 2 and 3 Modes 2 and 3 Programmer TBP-112A (EXPE = 1) (EXPE = 0) Mode D1/CPD1 * P61/FTOA/CIN1/ P61/FTOA/CIN1/KIN1/ KIN1/VSYNCO * VSYNCO/SUSPEND D2/CPD2 * P62/FTIA/CIN2/ P62/FTIA/CIN2/KIN2/ KIN2/VSYNCI * VSYNCI/TXENL...
Page 60 Section 1 Overview Pin No. Pin Name Extended Mode Single-Chip Mode Flash Memory Modes 2 and 3 Modes 2 and 3 Programmer TBP-112A (EXPE = 1) (EXPE = 0) Mode P40/IRQ0/TMI0/ExMCCLK P40/IRQ0/TMI0/ExMCCLK P41/IRQ1/TMI1/ExMCCMD/ P41/IRQ1/TMI1/ExMCCMD/ ExMCTxD/HSYNCI ExMCTxD/HSYNCI P42/IRQ2/TMO0/ExMCDAT/ P42/IRQ2/TMO0/ExMCDAT/ ExMCRxD ExMCRxD P43/IRQ3/TMO1/ P43/IRQ3/TMO1/ ExMCDATDIR/ExMCCSA/...
Page 61 Section 1 Overview Pin No. Pin Name Extended Mode Single-Chip Mode Flash Memory Modes 2 and 3 Modes 2 and 3 Programmer TBP-112A (EXPE = 1) (EXPE = 0) Mode P12/A2/CPA2 P12/PW2 P11/A1/CPA1 P11/PW1 P10/A0/CPA0 P10/PW0 P87/ExIRQ15/ADTRG/ExTMIY/ P87/ExIRQ15/ADTRG/ExTMIY/ USEXCL USEXCL P86/ExIRQ14/SCK2/ExTMIX P86/ExIRQ14/SCK2/ExTMIX D8/CPD8...
Page 62: Pin Functions
Section 1 Overview 1.3.3 Pin Functions Table 1.2 Pin Functions Pin No. Type Symbol TBP-112A Name and Function Power G8, G9 Input Power supply pins. Connect all these supply pins to the system power supply. Input Power supply pin. Connect this pin to VCC.
Page 63 Section 1 Overview Pin No. Type Symbol TBP-112A Name and Function Address A17 to A0 J8, K9 Output Address output pins G11, G10 F9, F11 F10, F8 E11, E10 D9, C10 B11, C9 B10, A10 D8, B9 Data bus D15 to D8 B6, A6 Input/ Upper bidirectional data bus...
Page 64 Section 1 Overview Pin No. Type Symbol TBP-112A Name and Function WAIT Input Requests insertion of a wait state in the control bus cycle when accessing an external 3- state address space. Output This pin is low when the external address space is being read from.
Page 65 Section 1 Overview Pin No. Type Symbol TBP-112A Name and Function PWM timer PW15 to PW0 G11, G10 Output PWM timer pulse output pins (PWM) F9, F11 F10, F8 E11, E10 D9, C10 B11, C9 B10, A10 D8, B9 14-bit PWX1 Output PWMX (D/A) pulse output pins...
Page 66 Section 1 Overview Pin No. Type Symbol TBP-112A Name and Function Serial TxD0 to TxD2 F2, C4 Output Transmit data output pins communi- cation RxD0 to RxD2 F1, B3 Input Receive data input pins Interface (SCI_0, SCK0 to SCK2 A5, D6 Input/ Clock input/output pins.
Page 67 Section 1 Overview Pin No. Type Symbol TBP-112A Name and Function AVCC K5, J6 Input Analog power supply pins for the A/D converter converter and D/A converter. When the A/D converter and D/A converter are not used, these pins should be connected to converter the system power supply.
Page 68 Section 1 Overview Pin No. Type Symbol TBP-112A Name and Function Multimedia ExMCCLK Output Common clock output pins for MMC mode * /SPI mode card MCCLK interface ExMCTxD Output Command/data output pins in SPI mode (MCIF) MCTxD ExMCRxD Input Response/data input pins in SPI mode MCRxD ExMCCSA Output...
Page 69 Section 1 Overview Pin No. Type Symbol TBP-112A Name and Function I/O ports P67 to P60 J5, H5 Input/ Eight input/output pins L4, K4 Output K3, H4 L2, K2 P77 to P72 H7, L8 Input Six input pins J7, K7 L7, H6 P87 to P80 A9, C8...
Page 70 Section 1 Overview Rev. 3.00 Jan 25, 2006 page 16 of 872 REJ09B0286-0300...
Page 71: Section 2 Cpu
Section 2 CPU Section 2 CPU The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2000 CPU.
Page 72: Differences Between H8S/2600 Cpu And H8S/2000 Cpu
Section 2 CPU  16 × 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W)  32 ÷ 16-bit register-register divide: 20 states (DIVXU.W) • Two CPU operating modes  Normal mode  Advanced mode • Power-down state  Transition to power-down state by SLEEP instruction ...
Page 73: Differences From H8/300 Cpu
Section 2 CPU 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers  Eight 16-bit extended registers and one 8-bit control register have been added. •...
Page 74: Cpu Operating Modes
Section 2 CPU CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte address space. The mode is selected by the LSI's mode pins. 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU in normal...
Page 75: Figure 2.1 Exception Vector Table (Normal Mode)
Section 2 CPU H'0000 Reset exception vector H'0001 H'0002 (Reserved for system use) H'0003 H'0004 H'0005 (Reserved for system use) H'0006 Exception H'0007 vector table H'0008 Exception vector 1 H'0009 H'000A Exception vector 2 H'000B Figure 2.1 Exception Vector Table (Normal Mode) (16 bits) CCR * (16 bits)
Page 76: Advanced Mode
Section 2 CPU 2.2.2 Advanced Mode • Address space Linear access to a maximum address space of 16 Mbytes is possible. • Extended registers (En) The extended registers (E0 to E7) can be used as 16-bit registers. They can also be used as the upper 16-bit segments of 32-bit registers or address registers.
Page 77: Figure 2.4 Stack Structure In Advanced Mode
Section 2 CPU The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode, the operand is a 32-bit longword operand, providing a 32-bit branch address.
Page 78: Address Space
Section 2 CPU Address Space Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product.
Page 79: Register Configuration
Section 2 CPU Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), and an 8-bit condition code register (CCR). General Registers (Rn) and Extended Registers (En) ER7 (SP) Control Registers...
Page 80: General Registers
Section 2 CPU 2.4.1 General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers.
Page 81: Program Counter (Pc)
Section 2 CPU Free area SP (ER7) Stack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched for read, the least significant PC bit is regarded as 0.) 2.4.3 Extended Control Register (EXR)
Page 82: Condition-Code Register (Ccr)
Section 2 CPU 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions.
Page 83: Initial Register Values
Section 2 CPU Bit Name Initial Value Description Undefined Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise. Undefined Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: •...
Page 84: Data Formats
Section 2 CPU Data Formats The H8S/2000 CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.
Page 85: Figure 2.9 General Register Data Formats (2)
Section 2 CPU Data Type Register Number Data Image Word data Word data Longword data Legend: : General register ER : General register E : General register R : General register RH : General register RL : Most significant bit : Least significant bit Figure 2.9 General Register Data Formats (2) Rev.
Page 86: Memory Data Formats
Section 2 CPU 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address.
Page 87: Instruction Set
Section 2 CPU Instruction Set The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as shown in table 2.1. Table 2.1 Instruction Classification Function Instructions Size Types Data transfer B/W/L POP * , PUSH * LDM, STM * MOVFPE * , MOVTPE *...
Page 88: Table Of Instructions Classified By Function
Section 2 CPU 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Operation Notation Symbol Description General register (destination) * General register (source) * General register * General register (32-bit register)
Page 89: Table 2.3 Data Transfer Instructions
Section 2 CPU Table 2.3 Data Transfer Instructions Size * Instruction Function (EAs) → Rd, Rs → (EAd) B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE Cannot be used in this LSI.
Page 90: Table 2.4 Arithmetic Operations Instructions (1)
Section 2 CPU Table 2.4 Arithmetic Operations Instructions (1) Instruction Size * Function Rd ± Rs → Rd, Rd ± #IMM → Rd B/W/L Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Subtraction on immediate data and data in a general register cannot be performed in bytes.
Page 91: Table 2.4 Arithmetic Operations Instructions (2)
Section 2 CPU Table 2.4 Arithmetic Operations Instructions (2) Instruction Size * Function Rd ÷ Rs → Rd DIVXS Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.
Page 92: Table 2.5 Logic Operations Instructions
Section 2 CPU Table 2.5 Logic Operations Instructions Instruction Size * Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data.
Page 93: Table 2.7 Bit Manipulation Instructions (1)
Section 2 CPU Table 2.7 Bit Manipulation Instructions (1) Instruction Size * Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Page 94: Table 2.7 Bit Manipulation Instructions (2)
Section 2 CPU Table 2.7 Bit Manipulation Instructions (2) Size * Instruction Function C ⊕ (<bit-No.> of <EAd>) → C BXOR Logically exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ⊕...
Page 95: Table 2.8 Branch Instructions
Section 2 CPU Table 2.8 Branch Instructions Instruction Size Function — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description Condition BRA (BT) Always (true) Always BRN (BF) Never (false) Never C ∨...
Page 96: Table 2.9 System Control Instructions
Section 2 CPU Table 2.9 System Control Instructions Size * Instruction Function TRAPA — Starts trap-instruction exception handling. — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR Moves the memory operand contents or immediate data to CCR or EXR.
Page 97: Basic Instruction Formats
Section 2 CPU Table 2.10 Block Data Transfer Instructions Instruction Size Function if R4L ≠ 0 then EEPMOV.B — Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next: if R4 ≠ 0 then EEPMOV.W — Repeat @ER5+ → @ER6+ R4–1 →...
Page 98: Addressing Modes And Effective Address Calculation
Section 2 CPU (1) Operation field only NOP, RTS (2) Operation field and register fields ADD.B Rn, Rm (3) Operation field, register fields, and effective address extension MOV.B @(d:16, Rn), Rm EA (disp) (4) Operation field, effective address extension, and condition field EA (disp) BRA d:16 Figure 2.11 Instruction Formats (Examples)
Page 99: Register Direct-Rn
Section 2 CPU Table 2.11 Addressing Modes Addressing Mode Symbol Register direct Register indirect @ERn Register indirect with displacement @(d:16,ERn)/@(d:32,ERn) Register indirect with post-increment @ERn+ Register indirect with pre-decrement @–ERn Absolute address @aa:8/@aa:16/@aa:24/@aa:32 Immediate #xx:8/#xx:16/#xx:32 Program-counter relative @(d:8,PC)/@(d:16,PC) Memory indirect @@aa:8 2.7.1 Register Direct—Rn...
Page 100: Absolute Address-@Aa:8, @Aa:16, @Aa:24, Or @Aa:32
Section 2 CPU Register Indirect with Pre-Decrement—@-ERn: The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word access, and 4 for longword access.
Page 101: Program-Counter Relative-@(D:8, Pc) Or @(D:16, Pc)
Section 2 CPU 2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC) This mode can be used by the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign-extended to 24 bits and added to the 24-bit address indicated by the PC value to generate a 24-bit branch address.
Page 102: Effective Address Calculation
Section 2 CPU 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode, the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Table 2.13 Effective Address Calculation (1) Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)
Page 103: Table 2.13 Effective Address Calculation (2)
Section 2 CPU Table 2.13 Effective Address Calculation (2) Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address Sign extension Immediate Operand is immediate data. PC contents Sign extension Memory contents Memory contents Rev. 3.00 Jan 25, 2006 page 49 of 872 REJ09B0286-0300...
Page 104: Processing States
Section 2 CPU Processing States The H8S/2000 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state transitions. • Reset state In this state the CPU and on-chip peripheral modules are all initialized and stopped. When the RES input goes low, all current processing stops and the CPU enters the reset state.
Page 105: Figure 2.13 State Transitions
Section 2 CPU End of bus request Bus request Program execution state SLEEP End of bus instruction request with SLEEP LSON = 0, instruction request SSBY = 0 with LSON = 0, PSS = 0, Bus-released state SSBY = 1 Request for End of exception...
Page 106: Usage Notes
Usage Notes 2.9.1 Note on TAS Instruction Usage The TAS instruction is not generated by the Renesas H8S and H8/300 series C/C++ compilers. The TAS instruction can be used as a user-defined intrinsic function. 2.9.2 Note on Bit Manipulation Instructions...
Page 107 Section 2 CPU BCLR instruction executed The BCLR instruction is executed for DDR in port 4 BCLR @P4DDR After executing BCLR Input/output Output Output Output Output Output Output Output Input Pin state High High level level level level level level level level [Description on Operation]...
Page 108: Eepmov Instruction
Section 2 CPU 2.9.3 EEPMOV Instruction 1. EEPMOV is a block-transfer instruction that transfers the byte size of data indicated by R4 * which starts from the address indicated by ER5, to the address indicated by ER6. ER5 + R4 * ER6 + R4 * 2.
Page 109: Section 3 Mcu Operating Modes
Section 3 MCU Operating Modes Section 3 MCU Operating Modes Operating Mode Selection This LSI supports two operating modes (modes 2 and 3). The operating mode is determined by the setting of the mode pins (MD2, MD1, and MD0). Table 3.1 shows the MCU operating mode selection.
Page 110: Mode Control Register (Mdcr)
Section 3 MCU Operating Modes 3.2.1 Mode Control Register (MDCR) MDCR is used to set an operating mode and to monitor the current operating mode. Bit Name Initial Value Description EXPE Extended Mode Enable Specifies extended mode. 0: Single-chip mode 1: Extended mode —...
Page 111: System Control Register (Syscr)
Section 3 MCU Operating Modes 3.2.2 System Control Register (SYSCR) SYSCR selects a system pin function, monitors a reset source, selects the interrupt control mode and the detection edge for NMI, enables or disables register access to the on-chip peripheral modules, and enables or disables on-chip RAM address space.
Page 112 Section 3 MCU Operating Modes Bit Name Initial Value Description NMIEG NMI Edge Select Selects the valid edge of the NMI interrupt input. 0: An interrupt is requested at the falling edge of NMI input 1: An interrupt is requested at the rising edge of NMI input KINWUE Keyboard Control Register Access Enable...
Page 113: Serial Timer Control Register (Stcr)
Section 3 MCU Operating Modes 3.2.3 Serial Timer Control Register (STCR) STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and selects the input clock of the timer counter. Bit Name Initial Value Description — R/(W) Reserved The initial value should not be changed.
Page 114: Operating Mode Descriptions
Section 3 MCU Operating Modes Bit Name Initial Value Description FLSHE Flash Memory Control Register Enable Enables or disables CPU access for flash memory registers (FLMCR1, FLMCR2, EBR1, EBR2), control registers of power-down states (SBYCR, LPWRCR, MSTPCRH, MSTPCRL), and control registers of on- chip peripheral modules (BCR2, WSCR2, PCSR, SYSCR2).
Page 115: Mode 3
Section 3 MCU Operating Modes 3.3.2 Mode 3 The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled. The CPU can access a 56-kbyte address space in mode 3. After a reset, the LSI is set to single-chip mode. To access an external address space, bit EXPE in MDCR should be set to 1.
Page 116: Address Map In Each Operating Mode
Section 3 MCU Operating Modes Address Map in Each Operating Mode Figures 3.1 and 3.2 show the address map in each operating mode. ROM: 256 kbytes, RAM: 10 kbytes ROM: 256 kbytes, RAM: 10 kbytes Mode 2 (EXPE = 1) Mode 2 (EXPE = 0) Advanced mode Advanced mode...
Page 117: Figure 3.2 Address Map (Mode 3)
Section 3 MCU Operating Modes ROM: 56 kbytes, RAM: 4 kbytes ROM: 56 kbytes, RAM: 4 kbytes Mode 3 (EXPE = 1) Mode 3 (EXPE = 0) Normal mode Normal mode Extended mode with Single-chip mode on-chip ROM H'0000 H'0000 On-chip ROM On-chip ROM H'DFFF...
Page 118 Section 3 MCU Operating Modes Rev. 3.00 Jan 25, 2006 page 64 of 872 REJ09B0286-0300...
Page 119: Section 4 Exception Handling
Section 4 Exception Handling Section 4 Exception Handling Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, interrupt, direct transition, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority.
Page 120: Exception Sources And Exception Vector Table
Section 4 Exception Handling Exception Sources and Exception Vector Table Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Table 4.2 Exception Handling Vector Table Vector Address Vector Exception Source Number Normal Mode Advanced Mode...
Page 121: Reset
Section 4 Exception Handling Vector Address Vector Exception Source Number Normal Mode Advanced Mode External interrupt KIN7 to KIN0 H'003C to H'003D H'000078 to H'00007B External interrupt KIN9, KIN8 H'003E to H'003F H'00007C to H'00007F Reserved for system use H'0040 to H'0041 H'000080 to H'000083 External interrupt WUE15 to WUE8...
Page 122: Reset Exception Handling
Section 4 Exception Handling 4.3.1 Reset Exception Handling When the RES pin goes high after being held low for the necessary time, this LSI starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized and the I bit is set to 1 in CCR.
Page 123: Interrupts After Reset
Section 4 Exception Handling 4.3.2 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset.
Page 124: Stack Status After Exception Handling
Section 4 Exception Handling The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.3 shows the status of CCR after execution of trap instruction exception handling. Table 4.3 Status of CCR after Trap Instruction Exception Handling Interrupt Control Mode...
Page 125: Usage Note
Section 4 Exception Handling Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed in words or longwords, and the value of the stack pointer (SP: ER7) should always be kept even.
Page 126 Section 4 Exception Handling Rev. 3.00 Jan 25, 2006 page 72 of 872 REJ09B0286-0300...
Page 127: Section 5 Interrupt Controller
Section 5 Interrupt Controller Section 5 Interrupt Controller Features • Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). • Priorities settable with ICR An interrupt control register (ICR) is provided for setting interrupt priorities.
Page 128: Figure 5.1 Block Diagram Of Interrupt Controller
Section 5 Interrupt Controller INTM1, INTM0 SYSCR NMIEG NMI input NMI input Interrupt request IRQ input IRQ input Vector number Priority level ISCR determination KMIMR WUEMR I, UI KIN input KIN, WUE WUE input input Internal interrupt sources SWDTEND to MMCIC Interrupt controller Legend: : Interrupt control register...
Page 129: Input/Output Pins
Section 5 Interrupt Controller Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Pin Configuration Symbol Function Input Nonmaskable external interrupt Rising edge or falling edge can be selected IRQ15 to IRQ0 Input Maskable external interrupts ExIRQ15 to ExIRQ2 Rising edge, falling edge, or both edges, or level sensing, can be selected individually for each pin.
Page 130: Interrupt Control Registers A To D (Icra To Icrd)
Section 5 Interrupt Controller 5.3.1 Interrupt Control Registers A to D (ICRA to ICRD) The ICR registers set interrupt control levels for interrupts other than NMI. The correspondence between interrupt sources and ICRA to ICRD settings is shown in table 5.2. Bit Name Initial Value Description...
Page 131: Address Break Control Register (Abrkcr)
Section 5 Interrupt Controller 5.3.2 Address Break Control Register (ABRKCR) ABRKCR controls the address breaks. When both the CMF flag and BIE flag are set to 1, an address break is requested. Bit Name Initial Value Description CMIF Undefined Condition Match Flag Address break source flag.
Page 132: Break Address Registers A To C (Bara To Barc)
Section 5 Interrupt Controller 5.3.3 Break Address Registers A to C (BARA to BARC) The BAR registers specify an address that is to be a break address. An address in which the first byte of an instruction exists should be set as a break address. In normal mode, addresses A23 to A16 are not compared.
Page 133: Irq Sense Control Registers (Iscr16H, Iscr16L, Iscrh, Iscrl)
Section 5 Interrupt Controller 5.3.4 IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL) The ISCR registers select the source that generates an interrupt request at pins IRQ15 to IRQ0 or pins ExIRQ15 to ExIRQ2. Switching between pins IRQ15 to IRQ2 and pins ExIRQ15 to ExIRQ2 is performed by means of IRQ sense port select register 16 (ISSR16) and the IRQ sense port select register (ISSR).
Page 134 Section 5 Interrupt Controller ISCRH Bit Name Initial Value Description IRQ7SCB IRQn Sense Control B IRQ7SCA IRQn Sense Control A 00: Interrupt request generated at low level of IRQ6SCB IRQn or ExIRQn input IRQ6SCA 01: Interrupt request generated at falling edge IRQ5SCB of IRQn or ExIRQn input IRQ5SCA...
Page 135: Irq Enable Registers (Ier16, Ier)
Section 5 Interrupt Controller 5.3.5 IRQ Enable Registers (IER16, IER) IERs control the enabling and disabling of interrupt requests IRQ15 to IRQ0. IER16 Bit Name Initial Value Description IRQ15E IRQn Enable (n = 15 to 8) IRQ14E The IRQn interrupt request is enabled when this IRQ13E bit is 1.
Page 136: Irq Status Registers (Isr16, Isr)
Section 5 Interrupt Controller 5.3.6 IRQ Status Registers (ISR16, ISR) The ISR registers are flag registers that indicate the status of IRQ15 to IRQ0 interrupt requests. ISR16 Bit Name Initial Value Description IRQ15F [Setting condition] IRQ14F When the interrupt source selected by the ISCR IRQ13F registers occurs IRQ12F...
Page 137: Keyboard Matrix Interrupt Mask Registers (Kmimra, Kmimr6) Wake-Up Event Interrupt Mask Register (Wuemr3)
Section 5 Interrupt Controller 5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR6) Wake-Up Event Interrupt Mask Register (WUEMR3) The KMIMR and WUEMR registers enable or disable wake-up key-sensing interrupt inputs (KIN9 to KIN0), and wake-up event interrupt inputs (WUE15 to WUE8). KMIMRA Bit Name Initial Value R/W...
Page 138: Interrupt Sources
Section 5 Interrupt Controller Interrupt Sources 5.4.1 External Interrupts There are four external interrupts: NMI, IRQ15 to IRQ0, KIN9 to KIN0 and WUE15 to WUE8. These interrupts can be used to restore this LSI from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits.
Page 139: Figure 5.2 Block Diagram Of Interrupts Irq15 To Irq0
Section 5 Interrupt Controller IRQnE IRQnSCA, IRQnSCB IRQnF IRQn interrupt Edge/level request detection circuit IRQn input or ExIRQn* input Clear signal Notes: n = 15 to 0 * ExIRQn stands for ExIRQ15 to ExIRQ2. Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0 KIN9 to KIN0 Interrupts, WUE15 to WUE8 Interrupts: Interrupts KIN9 to KIN0 and WUE15 to WUE8 are requested by an input signal at pins KIN9 to KIN0 and WUE15 to WUE8.
Page 140: Internal Interrupts
Section 5 Interrupt Controller KMIMn Falling-edge KINn interrupt request detection circuit KINn input Clear signal Note: n = 9 to 0 Figure 5.3 Block Diagram of Interrupts KIN9 to KIN0 and WUE15 to WUE8 (Example of KIN9 to KIN0) 5.4.2 Internal Interrupts Internal interrupts issued from the on-chip peripheral modules have the following features: •...
Page 141: Table 5.3 Interrupt Sources, Vector Addresses, And Interrupt Priorities
Section 5 Interrupt Controller Table 5.3 Interrupt Sources, Vector Addresses, and Interrupt Priorities Vector Address Origin of Vector Normal Advanced Interrupt Source Name Number Mode Mode Priority External pin NMI H'000E H'00001C — High IRQ0 H'0020 H'000040 ICRA7 IRQ1 H'0022 H'000044 ICRA6 IRQ2...
Page 142 Section 5 Interrupt Controller Vector Address Origin of Vector Normal Advanced Interrupt Source Name Number Mode Mode Priority ICIA (Input capture A) H'0060 H'0000C0 ICRB6 High ICIB (Input capture B) H'0062 H'0000C4 ICIC (Input capture C) H'0064 H'0000C8 ICID (Input capture D) H'0066 H'0000CC OCIA (Output compare A)
Page 143 Section 5 Interrupt Controller Vector Address Origin of Vector Normal Advanced Interrupt Source Name Number Mode Mode Priority SCI_2 ERI2 (Reception error 2) H'00B0 H'000160 ICRC5 High RXI2 (Reception completion 2) H'00B2 H'000164 TXI2 (Transmission data empty 2) H'00B4 H'000168 TEI2 (Transmission end 2) H'00B6 H'00016C...
Page 144: Interrupt Control Modes And Interrupt Operation
Section 5 Interrupt Controller Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: Interrupt control mode 0 and interrupt control mode 1. Interrupt operations differ depending on the interrupt control mode. NMI interrupts and address break interrupts are always accepted except for in reset state or in hardware standby mode. The interrupt control mode is selected by SYSCR.
Page 145: Table 5.5 Interrupts Acceptable In Each Interrupt Control Mode
Section 5 Interrupt Controller Interrupt Acceptance Control and 3-Level Control: In interrupt control modes 0 and 1, interrupt acceptance control and 3-level mask control is performed by means of the I and UI bits in CCR and ICR (control level). Table 5.5 shows the interrupts that can be accepted in each interrupt control mode.
Page 146: Interrupt Control Mode 0
Section 5 Interrupt Controller Table 5.6 Operations and Control Signal Functions in Each Interrupt Control Mode Interrupt Acceptance Control Setting Interrupt Default Priority 3-Level Control Control Mode Determination (Trace) INTM1 INTM0 — — — Legend: Interrupt operation control performed IM: Used as an interrupt mask bit PR: Sets priority —: Not used...
Page 147: Figure 5.5 Flowchart Of Procedure Up To Interrupt Acceptance In Interrupt Control
Section 5 Interrupt Controller 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Program excution state Interrupt generated? Hold pending An interrupt with interrupt...
Page 148: Interrupt Control Mode 1
Section 5 Interrupt Controller 5.6.2 Interrupt Control Mode 1 In interrupt control mode 1, mask control is applied to three levels for IRQ and on-chip peripheral module interrupt requests by comparing the I and UI bits in CCR in the CPU, and the ICR setting. Note however that the KIN, WUE, and DTI interrupt requests can be accepted when the I bit is cleared to 0 and are held pending when the I bit is set to 1.
Page 149 Section 5 Interrupt Controller Figure 5.7 shows a flowchart of the interrupt acceptance operation. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. According to the interrupt control level specified in ICR, the interrupt controller only accepts an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request with interrupt control level 0 (no priority).
Page 150: Interrupt Exception Handling Sequence
Section 5 Interrupt Controller Program excution state Interrupt generated? Hold pending An interrupt with interrupt control level 1? IRQ0 IRQ0 IRQ1 IRQ1 MMCIC MMCIC I = 0 I = 0 UI = 0 Save PC and CCR 1, UI Read vector address Branch to interrupt handling routine Figure 5.7 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1...
Page 151: Figure 5.8 Interrupt Exception Handling
Section 5 Interrupt Controller Figure 5.8 Interrupt Exception Handling Rev. 3.00 Jan 25, 2006 page 97 of 872 REJ09B0286-0300...
Page 152: Interrupt Response Times
Section 5 Interrupt Controller 5.6.4 Interrupt Response Times Table 5.7 shows interrupt response times—the intervals between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.7 are explained in table 5.8. Table 5.7 Interrupt Response Times No.
Page 153: Dtc Activation By Interrupt
Section 5 Interrupt Controller 5.6.5 DTC Activation by Interrupt The DTC can be activated by an interrupt. In this case, the following options are available: • Interrupt request to CPU • Activation request to DTC • Both of the above For details of interrupt requests that can be used to activate the DTC, see section 7, Data Transfer Controller (DTC).
Page 154: Table 5.9 Interrupt Source Selection And Clearing Control
Section 5 Interrupt Controller Operation Order: If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling. Table 5.9 summarizes interrupt source selection and interrupt source clearance control according to the settings of the DTCE bit of DTCERA to DTCERE in the DTC and the DISEL bit of MRB in the DTC.
Page 155: Usage Notes
Section 5 Interrupt Controller Usage Notes 5.7.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, and if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, so interrupt exception handling for that interrupt will be executed on completion of the instruction.
Page 156: Instructions That Disable Interrupts
Section 5 Interrupt Controller 5.7.2 Instructions that Disable Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions are executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit or UI bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends.
Page 157: Section 6 Bus Controller
Section 6 Bus Controller Section 6 Bus Controller This LSI has an on-chip bus controller (BSC) that manages the bus width and the number of access states of the external address space. The BSC also has a bus arbitration function, and controls the operation of the internal bus masters—CPU, data transfer controller (DTC), and RAM FIFO unit (RFU).
Page 158: Figure 6.1 Block Diagram Of Bus Controller
Section 6 Bus Controller Note: * CompactFlash (CompactFlash ) is a trademark of SanDisk Corporation in the United States, licensed through CFA (CompactFlash Association). Internal control signals External bus control signals controller Bus mode signal BCR2 WSCR WSCR2 Wait WAIT/CPWAIT controller CPU bus request signal DTC bus request signal...
Page 159: Input/Output Pins
Section 6 Bus Controller Input/Output Pins Table 6.1 summarizes the pins of the bus controller. Table 6.1 Pin Configuration Symbol Function Output Strobe signal indicating that address output on the address bus is enabled (when the IOSE bit in SYSCR is cleared to 0). Note that this signal is not output (the 256-kbyte expansion area is accessed while the CS256E bit in SYSCR is 1) or when the CP/CF expansion area is accessed (the CPCSE bit...
Page 160: Register Descriptions
Section 6 Bus Controller Register Descriptions The bus controller has the following registers. For details on the system control register, see section 3.2.2, System Control Register (SYSCR). • Bus control register (BCR) • Bus control register 2 (BCR2) • Wait state control register (WSCR) •...
Page 161 Section 6 Bus Controller Bit Name Initial Value Description BRSTS1 Burst Cycle Select 1 Selects the number of states in the burst cycle of the burst ROM interface. 0: 1 state 1: 2 states BRSTS0 Burst Cycle Select 0 Selects the number of words that can be accessed by burst access via the burst ROM interface.
Page 162: Bus Control Register 2 (Bcr2)
Section 6 Bus Controller 6.3.2 Bus Control Register 2 (BCR2) BCR2 is used to specify the access mode for the CP expansion area (basic mode) and CF expansion area (memory card mode). Bit Name Initial Value Description OWEAC OE/WE Assert Control Specifies the number of cycles from address output to the CPOE and CPWE signal assertion when the CF expansion area is specified as the CP expansion area.
Page 163 Section 6 Bus Controller Bit Name Initial Value Description ASTCP CP/CF Expansion Area Access State Control Selects the number of states for access to the CP/CF expansion area when the CPCSE bit in BCR2 is set to 1. This bit also enables or disables wait-state insertion. 0: 2-state access space.
Page 164: Wait State Control Register (Wscr)
Section 6 Bus Controller 6.3.3 Wait State Control Register (WSCR) WSCR is used to specify the data bus width for external address space access, the number of access states, the wait mode, and the number of wait states for access to external address spaces (basic expansion area and 256-kbyte expansion area).
Page 165 Section 6 Bus Controller Bit Name Initial Value Description Access State Control Selects the number of states for access to the basic expansion area. This bit also enables or disables wait- state insertion. 0: 2-state access space. Wait state insertion disabled in basic expansion area access 1: 3-state access space.
Page 166: Wait State Control Register 2 (Wscr2)
Section 6 Bus Controller 6.3.4 Wait State Control Register 2 (WSCR2) WSCR2 is used to specify the wait mode and number of wait states in access to the 256-kbyte expansion area and CP/CF expansion area. Bit Name Initial Value Description WMS10 256-kbyte Expansion Area Wait Mode Select 0 Selects the wait mode for access to the 256-kbyte...
Page 167: Bus Control
Section 6 Bus Controller Bit Name Initial Value Description WC22 CP/CF Expansion Area Wait Count 2−0 WC21 Select the number of program wait states to be inserted WC20 for access to the CP/CF expansion area when the CPCSE and ASTCP bits in BCR2 are set to 1. If the CP expansion area is selected, the WC22 bit must be cleared to 0.
Page 168 Section 6 Bus Controller Wait Mode and Number of Program Wait States: When a 3-state access space is designated by the AST bit in WSCR, the wait mode and the number of program wait states to be inserted automatically is selected by the WMS1, WMS0, WC1, and WC0 bits in WSCR. From 0 to 3 program wait states can be selected.
Page 169: Table 6.2 Address Ranges And External Address Spaces
Section 6 Bus Controller Table 6.2 Address Ranges and External Address Spaces Areas 256-kbyte Expansion Area, CP Expansion Area (Basic Mode), CF Expansion Area (Memory Address Range Basic Expansion Area Card Mode)  H'080000–H'F7FFFF No condition (15 Mbytes) When WAIT/CPWAIT pin ∆...
Page 170 Section 6 Bus Controller Areas 256-kbyte Expansion Area, CP Expansion Area (Basic Mode), CF Expansion Area (Memory Address Range Basic Expansion Area Card Mode)  H'(FF)F000–H'(FF)F7FF No condition When IOSE = 1, IOS is (2 kbytes) output and address pins A10 to A0 are used.
Page 171: Table 6.3 Bit Settings And Bus Specifications Of Basic Bus Interface
Section 6 Bus Controller Table 6.3 Bit Settings and Bus Specifications of Basic Bus Interface Areas CP Expansion Area (Basic Mode) and CF Expansion Area Basic Expansion 256-kbyte (Memory Card BRSTRM CS256E CPCSE Area Expansion Area Mode) — Basic expansion area Used as basic Used as basic expansion area...
Page 172: Table 6.4 Bus Specifications For Basic Expansion Area/Basic Bus Interface
Section 6 Bus Controller Table 6.4 Bus Specifications for Basic Expansion Area/Basic Bus Interface Bus Specifications Number of Number of Program Access Wait WMS1 WMS0 Bus Width States States — — — — — — Other than WMS1 = 0 and WMS0 = 1 —...
Page 173: Table 6.5 Bus Specifications For 256-Kbyte Expansion Area/Basic Bus Interface
Section 6 Bus Controller Table 6.5 Bus Specifications for 256-kbyte Expansion Area/Basic Bus Interface Bus Specifications Number of Number of Program Wait ABW256 AST256 WMS10 WC11 WC10 Bus Width Access States States — — — — — — — — —...
Page 174: Table 6.6 Bus Specifications For Cp Expansion Area (Basic Mode)/Basic Bus Interface
Section 6 Bus Controller Table 6.6 Bus Specifications for CP Expansion Area (Basic Mode)/Basic Bus Interface Bus Specifications Bus Width Number of Number of Access Program States Wait ABWCP ASTCP WMS21 WMS20 WC21 WC20 States — — — — — —...
Page 175: Advanced Mode
Section 6 Bus Controller Table 6.7 Bus Specifications for CF Expansion Area (Memory Card Mode)/Basic Bus Interface Bus Specifications Number of Number of Access Program ASTCP WMS21 WMS20 WC22 WC21 WC20 Bus Width States Wait States — — — — —...
Page 176: Normal Mode
Section 6 Bus Controller 6.4.3 Normal Mode The external address space is initialized as the basic bus interface and a 3-state access space. In mode 3 (normal mode), the address space other than on-chip ROM, on-chip RAM, internal I/O registers, and their reserved areas is specified as the external address space. The on-chip RAM area is enabled when the RAME bit in SYSCR is set to 1, and disabled and specified as the external address space when the RAME bit is cleared to 0.
Page 177: Basic Bus Interface
Section 6 Bus Controller Basic Bus Interface The basic bus interface enables direct connection to ROM and SRAM. For details on selection of the bus specifications for the basic expansion area, 256-kbyte expansion area, and CP/CF expansion area when using the basic bus interface, see tables 6.4 to 6.6. 6.5.1 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword.
Page 178: Valid Strobes
Section 6 Bus Controller Upper data bus Lower data bus D8 D7 Byte size • Even address Byte size • Odd address Word size Longword 1st bus cycle size 2nd bus cycle Figure 6.4 Access Sizes and Data Alignment Control (16-bit Access Space) 6.5.2 Valid Strobes Table 6.9 shows the data buses used and valid strobes for each access space.
Page 179: Basic Operation Timing
Section 6 Bus Controller 6.5.3 Basic Operation Timing 8-Bit, 2-State Access Space: Figure 6.5 shows the bus timing for an 8-bit, 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states cannot be inserted.
Page 180: Figure 6.6 Bus Timing For 8-Bit, 3-State Access Space
Section 6 Bus Controller 8-Bit, 3-State Access Space: Figure 6.6 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states can be inserted.
Page 181: Figure 6.7 Bus Timing For 16-Bit, 2-State Access Space (Even Byte Access)
Section 6 Bus Controller 16-Bit, 2-State Access Space: Figures 6.7 to 6.9 show bus timings for a 16-bit, 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the lower half (D7 to D0) for odd addresses.
Page 182: Figure 6.8 Bus Timing For 16-Bit, 2-State Access Space (Odd Byte Access)
Section 6 Bus Controller Bus cycle φ Address bus AS/IOS (IOSE = 1) CS256 (CS256E = 1) CPCS1 (CPCSE = 1 and CFE = 0) AS/IOS (IOSE = 0) D15 to D8 Invalid Read D7 to D0 Valid High level Write D15 to D8 Undefined...
Page 183: Figure 6.9 Bus Timing For 16-Bit, 2-State Access Space (Word Access)
Section 6 Bus Controller Bus cycle φ Address bus AS/IOS (IOSE = 1) CS256 (CS256E = 1) CPCS1 (CPCSE = 1 and CFE = 0) AS/IOS * (IOSE = 0) D15 to D8 Read Valid D7 to D0 Valid Write D15 to D8 Valid D7 to D0...
Page 184: Figure 6.10 Bus Timing For 16-Bit, 3-State Access Space (Even Byte Access)
Section 6 Bus Controller 16-Bit, 3-State Access Space: Figures 6.10 to 6.12 show bus timings for a 16-bit, 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the lower half (D7 to D0) for odd addresses.
Page 185: Figure 6.11 Bus Timing For 16-Bit, 3-State Access Space (Odd Byte Access)
Section 6 Bus Controller Bus cycle φ Address bus AS/IOS (IOSE = 1) CS256 (CS256E = 1) CPCS1 (CPCSE = 1 and CFE = 0) AS/IOS * (IOSE = 0) D15 to D8 Read Invalid D7 to D0 Valid High level Write D15 to D8 Undefined...
Page 186: Figure 6.12 Bus Timing For 16-Bit, 3-State Access Space (Word Access)
Section 6 Bus Controller Bus cycle φ Address bus AS/IOS (IOSE = 1) CS256 (CS256E = 1) CPCS1 (CPCSE = 1 and CFE = 0) AS/IOS * (IOSE = 0) D15 to D8 Valid Read D7 to D0 Valid Write D15 to D8 Valid D7 to D0...
Page 187: Wait Control
Section 6 Bus Controller 6.5.4 Wait Control When accessing the external address space, this LSI can extend the bus cycle by inserting one or more wait states (T ). There are three ways of inserting wait states: Program wait insertion, pin wait insertion using the WAIT/CPWAIT pin, and the combination of program wait and the WAIT/CPWAIT pin.
Page 188: Burst Rom Interface
Section 6 Bus Controller By WAIT/CPWAIT pin By program wait φ WAIT/CPWAIT Address bus AS/IOS (IOSE = 0) CPCS1 (CPCSE = 1 and CFE = 0) AS/IOS * (IOSE = 0) Read Data bus Read data Write Data bus Write data Notes: ↓...
Page 189: Basic Operation Timing
Section 6 Bus Controller 6.6.1 Basic Operation Timing The number of access states in the initial cycle (full access) of the burst ROM interface is determined by the AST bit in WSCR. When the AST bit is set to 1, wait states can be inserted. 1 or 2 states can be selected for burst access according to the setting of the BRSTS1 bit in BCR.
Page 190: Wait Control
Section 6 Bus Controller Full access Burst access φ Only lower Address bus address changes AS/IOS (IOSE = 0) Data bus Read data Read data Read data Figure 6.15 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0) 6.6.2 Wait Control As with the basic bus interface, program wait insertion or pin wait insertion using the WAIT pin...
Page 191: Memory Card Interface
Section 6 Bus Controller Memory Card Interface A CP expansion area can be set to the CF expansion area (memory card mode) by setting both the CPCSE bit in BCR2 to 1 and the CFE bit in BCR to 1. In memory card mode, the bus width is fixed to 16 bits.
Page 192: Valid Strobes
Section 6 Bus Controller 6.7.2 Valid Strobes Table 6.10 shows the data buses used and valid strobes. Table 6.10 Data Buses Used and Valid Strobes C C C C PCS1 PCS1 CPCS2 CPCS2 PCS1 PCS1 CPCS2 CPCS2 Access Read/ Valid Upper Data Bus Lower Data Size...
Page 193: Figure 6.17 Access Timing In Memory Card Mode (Basic Cycle)
Section 6 Bus Controller Bus cycle φ Address bus CPCS1, CPCS2 CPOE Read D15 to D0 Valid CPWE Write D15 to D0 Valid Figure 6.17 Access Timing in Memory Card Mode (Basic Cycle) By program wait φ Address bus CPCS1, CPCS2 CPOE Read D15 to D0...
Page 194: Wait Control
Section 6 Bus Controller 6.7.4 Wait Control With memory card interface, there are two ways of inserting wait states: Program wait insertion and pin wait insertion using the CPWAIT pin. Program Wait Mode: A specified number of wait states T can be inserted between the T state and T...
Page 195: Idle Cycle
Section 6 Bus Controller Idle Cycle When this LSI accesses the external address space, it can insert a 1-state idle cycle (T ) between bus cycles when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM with a long output floating time, and high-speed memory and I/O interfaces.
Page 196: Bus Arbitration
Section 6 Bus Controller Table 6.11 shows the pin states in an idle cycle. Table 6.11 Pin States in Idle Cycle Pins Pin State A17 to A0 Contents of immediately following bus cycle D15 to D0 High impedance AS, IOS, CS256, CPCS1, CPCS2 High RD, CPOE High...
Page 197: Bus Transfer Timing
Section 6 Bus Controller 6.9.2 Bus Transfer Timing When a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately.
Page 198 Section 6 Bus Controller Rev. 3.00 Jan 25, 2006 page 144 of 872 REJ09B0286-0300...
Page 199: Section 7 Data Transfer Controller (Dtc)
Section 7 Data Transfer Controller (DTC) Section 7 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. Figure 7.1 shows a block diagram of the DTC. The DTC's register information is stored in the on- chip RAM.
Page 200: Register Descriptions
Section 7 Data Transfer Controller (DTC) Internal address bus Interrupt controller On-chip RAM Interrupt request CPU interrupt Internal data bus request Legend: MRA, MRB : DTC mode register A, B CRA, CRB : DTC transfer count register A, B : DTC source address register : DTC destination register DTCERA to DTCERE : DTC enable registers A to E...
Page 201: Dtc Mode Register A (Mra)
Section 7 Data Transfer Controller (DTC) • DTC enable registers (DTCER) • DTC vector register (DTVECR) 7.2.1 DTC Mode Register A (MRA) MRA selects the DTC operating mode. Bit Name Initial Value Description Undefined — Source Address Mode 1, 0 Undefined —...
Page 202: Dtc Mode Register B (Mrb)
Section 7 Data Transfer Controller (DTC) Bit Name Initial Value Description Undefined — DTC Data Transfer Size Specifies the size of data to be transferred. 0: Byte-size transfer 1: Word-size transfer Legend: X: Don't care 7.2.2 DTC Mode Register B (MRB) MRB selects the DTC operating mode.
Page 203: Dtc Source Address Register (Sar)
Section 7 Data Transfer Controller (DTC) 7.2.3 DTC Source Address Register (SAR) SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 7.2.4 DTC Destination Address Register (DAR) DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC.
Page 204: Dtc Enable Registers (Dtcer)
Section 7 Data Transfer Controller (DTC) 7.2.7 DTC Enable Registers (DTCER) DTCER specifies DTC activation interrupt sources. DTCER is comprised of five registers: DTCERA to DTCERE. The correspondence between interrupt sources and DTCE bits is shown in tables 7.1 to 7.3. For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. Multiple DTC activation sources can be set at one time (only at the initial setting) by masking all interrupts and writing data after executing a dummy read on the relevant register.
Page 205: Dtc Vector Register (Dtvecr)
Section 7 Data Transfer Controller (DTC) 7.2.8 DTC Vector Register (DTVECR) DTVECR enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. Bit Name Initial Value Description SWDTE DTC Software Activation Enable Setting this bit to 1 activates DTC. Only 1 can be written to this bit.
Page 206: Activation Sources
Section 7 Data Transfer Controller (DTC) Activation Sources The DTC is activated by an interrupt request or by a write to DTVECR by software. The interrupt request source to activate the DTC is selected by DTCER. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the interrupt flag that became the activation source or the corresponding DTCER bit is cleared.
Page 207: Location Of Register Information And Dtc Vector Table
Section 7 Data Transfer Controller (DTC) Location of Register Information and DTC Vector Table Locate the register information in the on-chip RAM (addresses: H'(FF)EC00 to H'(FF)EFFF). Register information should be located at an address that is a multiple of four within the range. The method for locating the register information in address space is shown in figure 7.3.
Page 208: Table 7.2 Interrupt Sources, Dtc Vector Addresses, And Corresponding Dtces
Section 7 Data Transfer Controller (DTC) Table 7.2 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Activation Vector DTC Vector DTCE * Source Origin Activation Source Number Address Priority H'0400 + (vector Software Write to DTVECR DTVECR — High number × 2) External pins IRQ0 H'0420...
Page 209 Section 7 Data Transfer Controller (DTC) Activation Vector DTC Vector DTCE * Source Origin Activation Source Number Address Priority IIC_1 IICM1 H'04C2 DTCED4 High IICR1 H'04C4 DTCED3 IICT1 H'04C6 DTCED2  Reserved for system use H'04D0 DTCEE3 Reserved for system use H'04D2 DTCEE2 Reserved for system use...
Page 210: Operation
Section 7 Data Transfer Controller (DTC) Operation The DTC stores register information in on-chip RAM. When activated, the DTC reads register information in on-chip RAM and transfers data. After the data transfer, the DTC writes updated register information back to on-chip RAM. The pre-storage of register information in memory makes it possible to transfer data over any required number of channels.
Page 211: Normal Mode
Section 7 Data Transfer Controller (DTC) 7.5.1 Normal Mode In normal mode, one activation source transfers one byte or one word of data. Table 7.3 lists the register functions in normal mode. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have been completed, a CPU interrupt can be requested.
Page 212: Repeat Mode
Section 7 Data Transfer Controller (DTC) 7.5.2 Repeat Mode In repeat mode, one activation source transfers one byte or one word of data. Table 7.4 lists the register functions in repeat mode. From 1 to 256 transfers can be specified. Once the specified number of transfers have completed, the initial states of the transfer counter and the address register that is specified as the repeat area is restored, and transfer is repeated.
Page 213: Block Transfer Mode
Section 7 Data Transfer Controller (DTC) 7.5.3 Block Transfer Mode In block transfer mode, one activation source transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. Table 7.5 lists the register functions in block transfer mode.
Page 214: Chain Transfer
Section 7 Data Transfer Controller (DTC) 7.5.4 Chain Transfer Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently.
Page 215: Interrupts
Section 7 Data Transfer Controller (DTC) 7.5.5 Interrupts An interrupt request is issued to the CPU when the DTC has completed the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated.
Page 216: Figure 7.10 Dtc Operation Timing (Example Of Block Transfer Mode, With Block Size Of 2)
Section 7 Data Transfer Controller (DTC) φ DTC activation request DTC request Data transfer Vector read Address Read Write Read Write Transfer information Transfer information read write Figure 7.10 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2) φ...
Page 217: Number Of Dtc Execution States
Section 7 Data Transfer Controller (DTC) 7.5.7 Number of DTC Execution States Table 7.6 lists the execution status for a single DTC data transfer, and table 7.7 shows the number of states required for each execution status. Table 7.6 DTC Execution Status Register Information Internal Vector Read...
Page 218: Procedures For Using Dtc
Section 7 Data Transfer Controller (DTC) Procedures for Using DTC 7.6.1 Activation by Interrupt The procedure for using the DTC with interrupt activation is as follows: 1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM. 2.
Page 219: Software Activation
Section 7 Data Transfer Controller (DTC) SCI’s RDR address in SAR, the start address of the RAM area where the data will be received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value. 2. Set the start address of the register information at the DTC vector address. 3.
Page 220: Usage Notes
Section 7 Data Transfer Controller (DTC) Usage Notes 7.8.1 Module Stop Mode Setting DTC operation can be enabled or disabled by the module stop control register (MSTPCR). In the initial state, DTC operation is enabled. Access to DTC registers are disabled when module stop mode is set.
Page 221: Section 8 Ram-Fifo Unit (Rfu)
Section 8 RAM-FIFO Unit (RFU) Section 8 RAM-FIFO Unit (RFU) This LSI incorporates a RAM-FIFO unit (RFU). The RFU is activated by a request from the peripheral modules and can transfer data between the peripheral modules and on-chip RAM. As the RFU can specify the RAM address to be transferred by using a pointer that is updated for every data transfer execution, the RAM specified area can be regarded as an FIFO.
Page 222: Figure 8.1 Block Diagram Of Rfu
Section 8 RAM-FIFO Unit (RFU) Internal data bus Internal address bus RFU activation request Internal data bus interface Pointer set 0 BAR_0 RAR_0 TMP_0 WAR_0 DTCRA_0 DTCRB_0 DTSTRC_0 DTIDR_0 Pointer set 1* Pointer set 2* Pointer set 3* DATAN/FREEN NRA/NWA DTCRC DTCRD DTSTRA...
Page 223: Register Descriptions
Section 8 RAM-FIFO Unit (RFU) Register Descriptions The RFU has the following registers. • FIFO status/register/pointer (FSTR) Base address register (BAR) Read address pointer (RAR) Write address pointer (WAR) Temporary pointer (TMP) Valid data byte number (DATAN) Free area byte number (FREEN) Read start address (NRA) Write start address (NWA) •...
Page 224: Base Address Register (Bar)
Section 8 RAM-FIFO Unit (RFU) 8.2.2 Base Address Register (BAR) BAR is a 16-bit register provided in each pointer set, and allocated to bits 19 to 4 in FSTR. The base address should be set at the boundary specified by the BUD2 to BUD0 bits in DTCRA. Otherwise, address specification by the pointer and status display by calculation inter-pointers may not be performed correctly.
Page 225: Write Address Pointer (War)
Section 8 RAM-FIFO Unit (RFU) 8.2.4 Write Address Pointer (WAR) WAR is an 11-bit pointer provided in each pointer set, and allocated to bits 10 to 0 in FSTR. Bit Name Initial Value Description — All 0 Write Addresses 31 to 11 These bits are always read as 0 and cannot be modified.
Page 226: Valid Data Byte Number (Datan)
Section 8 RAM-FIFO Unit (RFU) 8.2.6 Valid Data Byte Number (DATAN) DATAN is 11-bit status data allocated to bits 10 to 0 in FSTR. Bit Name Initial Value Description — All 0 Reserved These bits are always read as 0 and cannot be modified.
Page 227: Write Start Address (Nwa)
Section 8 RAM-FIFO Unit (RFU) 8.2.9 Write Start Address (NWA) NWA is 32-bit status data allocated to bits 31 to 0 in FSTR. Bit Name Initial Value Description — Undefined Write Start Addresses 31 to 0 The RAM address is calculated by BAR + WAR 8.2.10 Data Transfer Control Register A (DTCRA) DTCRA is a register provided in each pointer set that controls the operation of each pointer set.
Page 228 Section 8 RAM-FIFO Unit (RFU) Bit Name Initial Value Description BUD2 Boundary 2 to 0 BUD1 These bits select the FIFO size and the BUD0 existence of boundary overflow. 000: 32 bytes 001: 64 bytes 010: 128 bytes 011: 256 bytes 100: 512 bytes 101: 1024 bytes 110: 2048 bytes...
Page 229: Data Transfer Control Register B (Dtcrb)
Section 8 RAM-FIFO Unit (RFU) 8.2.11 Data Transfer Control Register B (DTCRB) DTCRB is a register provided in each pointer set that controls the operation of the interrupt flag in each pointer set and the data transfer between pointers. Bit Name Initial Value Description BOVF_RE...
Page 230: Data Transfer Status Register C (Dtstrc)
Section 8 RAM-FIFO Unit (RFU) Bit Name Initial Value Description LOAD Pointer Reload If this bit is set to 1 when the TMP settings are made, this bit copies the contents of TMP to RAR or WAR. When the read temporary pointer is used, the contents of TMP are copied to RAR.
Page 231 Section 8 RAM-FIFO Unit (RFU) Bit Name Initial Value Description BOVF_R R/(W) Boundary Overflow (at reading) Indicates detection of boundary overflow in RAR or TMP (when the read temporary pointer is selected). This flag can be masked by the BOVF_RE bit in DTCRB. BOVF_W R/(W) Boundary Overflow (at writing)
Page 232: Data Transfer Id Register (Dtidr)
Section 8 RAM-FIFO Unit (RFU) 8.2.13 Data Transfer ID Register (DTIDR) DTIDR is a register provided in each pointer set. DTIDR selects the peripheral module, which is an activation source of each pointer set. A 4-bit ID has been assigned to the peripheral modules. DTIDR selects two IDs. The ID selected by DTIDR is enabled by setting the IDE-A and IDE-B bits in DTCRA to 1.
Page 233: Data Transfer Id Read/Write Select Register B (Dtidsrb)
Section 8 RAM-FIFO Unit (RFU) 8.2.15 Data Transfer ID Read/Write Select Register B (DTIDSRB) DTIDSRB selects the direction for transferring ID7 to ID0. As IDs have already been assigned for the peripheral modules, the transfer direction is fixed. For details, refer to section 8.8, Operation. Bit Name Initial Value Description...
Page 234: Data Transfer Status Register B (Dtstrb)
Section 8 RAM-FIFO Unit (RFU) 8.2.17 Data Transfer Status Register B (DTSTRB) DTSTRB includes error interrupt flags for each pointer set. Bit Name Initial Value Description 7 to 4 — All 0 R/(W) Reserved The initial value should not be changed. R/(W) * DTEF3 Data Transfer Error Interrupt Flags 3 to 1...
Page 235: Data Transfer Control Register D (Dtcrd)
Section 8 RAM-FIFO Unit (RFU) 8.2.19 Data Transfer Control Register D (DTCRD) DTCRD includes enable bits for each pointer set. When the DTE bit is cleared to 0 and then reset to 1, the empty information is restored. Bit Name Initial Value Description 7 to 4...
Page 236 Section 8 RAM-FIFO Unit (RFU) Bit Name Initial Value Description CHS2 Pointer Number Select CHS1 These bits represent the pointer set number to CHS0 be accessed from FSTR, DTCRA, DTCRB, DTIDR, and DTSTRC. Register Select Selects whether to access register/pointer or FIFO status by FSTR.
Page 237: Activation Source And Priority
Section 8 RAM-FIFO Unit (RFU) Activation Source and Priority The RFU operates upon a request from the peripheral modules regarding it as an activation source. In SCI, the request from the peripheral modules is an event that indicates 1-byte data transfer completion, such as setting the TDRE and RDRF bits.
Page 238: Ram-Fifo Location
Section 8 RAM-FIFO Unit (RFU) RAM-FIFO Location The RAM-FIFO should be allocated at the addresses H'(FF)E080 to H'(FF)EFFF and H'FF0800 to H'FF1FFF in on-chip RAM. Do not allocate the RAM-FIFO at the external address space. RAM-FIFO Pointer The RAM-FIFO specifies the start address by BAR, and the size by the BUD2 to BUD0 bits in DTCRA.
Page 239: Table 8.3 Rfu Bus Cycle Types
Section 8 RAM-FIFO Unit (RFU) All peripheral modules perform a handshake following data transfer to update the pointer, depending on approval/refusal of the handshake. In this case, TMP is used during data transfer until a handshake. When the handshake is approved, the contents of RAR/WAR are regarded as the formal contents of the pointer, and are sent to TMP (mark operation).
Page 240: Table 8.4 Requests From Peripheral Modules And Rfu Bus Cycle
Section 8 RAM-FIFO Unit (RFU) Table 8.4 Requests from Peripheral Modules and RFU Bus Cycle Requests from Transfer Condition and FIFO Pointer RFU Bus Cycle Pointer Peripheral Modules Status Contents Manipulation RAM → peripheral Data transfer Other than RAM read, peripheral Adds RAR modules the following...
Page 241 Section 8 RAM-FIFO Unit (RFU) Requests from Transfer Condition and FIFO Pointer RFU Bus Cycle Pointer Peripheral Modules Status Contents Manipulation Pointer mark TMP is not used Acknowledge only No pointer manipulations RAR → TMP TMP is used as a read temporary pointer Acknowledge only WAR →...
Page 242: Rfu Bus Cycle
Section 8 RAM-FIFO Unit (RFU) RFU Bus Cycle 8.7.1 Clock Division As this LSI supports medium-speed mode, current consumption can be reduced by dividing the operating clock of the bus master. On the other hand, high-speed response may be requested of the RFU, which is one of the bus masters.
Page 243: Rfu Bus Cycle Insertion
Section 8 RAM-FIFO Unit (RFU) 8.7.2 RFU Bus Cycle Insertion The RFU bus cycle can be inserted at a break in the bus cycle under almost all conditions. Table 8.5 summarizes a comparison of enabling/disabling bus cycle insertion for the DTC and RFU.
Page 244: Figure 8.3 Example Of Rfu Response Time
Section 8 RAM-FIFO Unit (RFU) • RFU bus cycle: 2 states • Cycle to synchronize the RFU signal with the peripheral module clock: 1 and 2 states (depending on the peripheral module clock) The total of the above cycles is 5 to 13 states. Cycles for synchronization of the peripheral module clock with the system clock are needed even when the hardware FIFO is used instead of the RFU.
Page 245: Operation
Section 8 RAM-FIFO Unit (RFU) Operation The RFU is presupposed to operate with the following procedure: • Enable ID to be written to the RFU, and store data received by the peripheral module into FIFO. • Enable ID to be read from the RAM-FIFO, and supply data transmitted by the peripheral module from FIFO.
Page 246: Transmission/Reception Of Consecutive Data Blocks
Section 8 RAM-FIFO Unit (RFU) Table 8.6 Settings when Using Boundary Overflow (Transmission/Reception of Single Data Block) RAM → → → → Peripheral Peripheral Modules → → → → RAM Transfer Condition Modules Number of transfer data bytes — FIFO size BUD2 to BUD0 Base address Clear the bits lower...
Page 247: Rfu Manipulation By Usb
Section 8 RAM-FIFO Unit (RFU) the FIFO size. Programming should be such that the CPU access does not deviate from the FIFO area. 8.8.3 RFU Manipulation by USB Figure 8.4 is a block diagram of the RFU interface in the USB. The USB can use the RFU for data transfer with end point 4 (EP4) and end point 5 (EP5).
Page 248: Figure 8.4 Rfu Interface Of Usb
Section 8 RAM-FIFO Unit (RFU) USB host (12 Mbps) Function core section (USB protocol processing section) Transmission Transmission data (12 MHz) data (12 MHz) EP4 transmit buffer EP5 receive buffer (2-byte buffer) (2-byte buffer) Transmisison data Reception data (8 MHz to 24 MHz) (8 MHz to 24 MHz) Internal data bus Data area for...
Page 249: Figure 8.5 Operation Flow Of Usb In Transfer
Section 8 RAM-FIFO Unit (RFU) Hardware (USB, RFU) Firmware (CPU) IDLE Receive IN token Start USBID interrupt handling From the host Read USBIFR0 and USBIFR1 Is EP4 stalled? to judge an interrupt source The case of 0 data packet transmission can be regarded as look-ahead processing Read TSFR0 to confirm...
Page 250: Figure 8.6 Operation Flow Of Usb Out Transfer
Section 8 RAM-FIFO Unit (RFU) Hardware (USB, RFU) Firmware (CPU) IDLE Start USBID interrupt handling Receive OUT token from the host Read from USBIFR0 and USBIFR1 to judge an interrupt source Is EP5 stalled? UDTR Read TSFR0 to confirm Read TFFR0 to confirm Read UDTRFR to confirm the EP5TS interrupt the EP5TF interrupt...
Page 251: Rfu Manipulation By Sci
Section 8 RAM-FIFO Unit (RFU) 8.8.4 RFU Manipulation by SCI Figure 8.7 is a block diagram of the RFU interface in the SCI. The SCI can use the RFU for data transmission and reception. The RFU is activated by setting the TDRE flag and the RDRF flag. Figure 8.8 shows the operational flow for transmission.
Page 252: Figure 8.8 Operation Flow Of Sci Transmission
Section 8 RAM-FIFO Unit (RFU) Prepare transmit data in RAM Initialize the RFU Initialize the SCI Set TDRE_DTE in SCIDTER to 1 Set TE in SCR to 1 RFU activation request Overread RAM data? Transfer transmit data from RAM to TDR Start transmission TDRE = 1 TDRE_DTE in SCIDTER are...
Page 253: Figure 8.9 Operation Flow Of Sci Reception
Section 8 RAM-FIFO Unit (RFU) Initialize the RFU Initialize the SCI Set RDRF_DTE in SCIDTER to 1 Set RE in SCR to 1 Start reception RDRF = 1 RFU activation request Overwrite RAM? Transfer receive data from RDR to RAM RDRF_DTE in SCIDTER are automatically cleared to 0 Figure 8.9 Operation Flow of SCI Reception...
Page 254: Rfu Manipulation By Mcif
Section 8 RAM-FIFO Unit (RFU) 8.8.5 RFU Manipulation by MCIF Figure 8.10 is a block diagram of the RFU interface in the MCIF. The MCIF can use the RFU for data transmission and reception. Figure 8.11 shows the operational flow for transmission. When the transmitted data is written to the RFU, and start of transmission is triggered (the DATAEN bit in OPCR is set), the MCIF issues a data transfer request to the RFU.
Page 255: Figure 8.11 Operation Flow Of Mcif Transmission
Section 8 RAM-FIFO Unit (RFU) When the RFU is emptied during data transmission, the transmission resume trigger (the DATAEN bit in OPCR is set) is set once the RFU empty is cancelled (after the necessary data is written), and data transmission is resumed. When data reception is started, data is automatically written to the RFU.
Page 256: Interrupt Sources
Section 8 RAM-FIFO Unit (RFU) Hardware (MCIF, RFU) Firmware (CPU) Command transmission Command transmission (data transmission to multimedia card) (data reception from multimedia card) Data start bit received? Data reception command FIFO full sequence ended? 1-byte data reception from multimedia card Card clock stop FIFO full cancellation (reception halted)
Page 257: Rfu Initialization
Section 8 RAM-FIFO Unit (RFU) 8.10 RFU Initialization Figure 8.13 shows the initialization flow of the RFU. Clear DTE bit in DTCRD Disable the relevant pointer set Clear the pointer Clear RAR, WAR, TMP Clear DTSTRA, DTSTRB, DTSTRC Clear each setting Set the base address Set BAR Transfer word/byte data and...
Page 258: Usage Notes
Section 8 RAM-FIFO Unit (RFU) 8.11 Usage Notes 1. Conflict between CPU write to DTRSR and RFU activation request If conflict occurs between a CPU write to the RS bit in DTRSR while it is 0 and an RFU activation request, data transfer by the RFU cannot be performed correctly. In order to access the FIFO state, the RS bit must be set to 1 at RFU initialization in advance.
Page 259: Section 9 I/O Ports
Section 9 I/O Ports Section 9 I/O Ports Table 9.1 is a summary of the port functions. The pins of each port also function as input/output pins of peripheral modules and interrupt input pins. Each input/output port includes a data direction register (DDR) that controls input/output and a data register (DR) that stores output data.
Page 260 Section 9 I/O Ports Extended Mode Single-Chip Mode Port Description I/O Status Mode 2, Mode 3 Mode 2, Mode 3 (EXPE = 1) (EXPE = 0) Port General I/O port D15/CPD15 P37/WUE15 Built-in input also functioning pull-up MOSs D14/CPD14 P36/WUE14 as bidirectional LED drive D13/CPD13...
Page 261 Section 9 I/O Ports Extended Mode Single-Chip Mode Port Description I/O Status Mode 2, Mode 3 Mode 2, Mode 3 (EXPE = 1) (EXPE = 0) D7/CPD7 * Port General I/O port P67/CIN7/ P67/CIN7/KIN7/DPLS Built-in input KIN7 * also functioning pull-up MOSs as bidirectional D6/CPD6 *...
Page 262 Section 9 I/O Ports Extended Mode Single-Chip Mode Port Description I/O Status Mode 2, Mode 3 Mode 2, Mode 3 (EXPE = 1) (EXPE = 0) Port General I/O port P87/ExIRQ15/ADTRG/ExTMIY/USEXCL P87 to P80 also functioning are NMOS P86/ExIRQ14/SCK2/ExTMIX as A/D converter push-pull P85/ExIRQ13/SCK1/ExTMI1 external trigger...
Page 263: Port 1
Section 9 I/O Ports Port 1 Port 1 is an 8-bit I/O port. Port 1 pins also function as an address bus, PWM output pins, and CompactFlash address output pins. Port 1 functions change according to the operating mode. Port 1 has the following registers.
Page 264: Port 1 Data Register (P1Dr)
Section 9 I/O Ports 9.1.2 Port 1 Data Register (P1DR) P1DR stores output data for the port 1 pins. Bit Name Initial Value Description P17DR P1DR stores output data for the port 1 pins that are used as the general output port. P16DR If a port 1 read is performed while the P1DDR bits P15DR...
Page 265: Pin Functions
Section 9 I/O Ports 9.1.4 Pin Functions The relationship between register setting values and pin functions are as follows in each operating mode. In the tables, the symbol “—” stands for Don't care. Extended Mode: The function of port 1 pins is switched as shown below according to the P1nDDR bit. P1nDDR Pin function P17 to P10 input pins...
Page 266: Port 2
Section 9 I/O Ports Port 2 Port 2 is an 8-bit I/O port. Port 2 pins also function as an address bus, PWM output pins, and CompactFlash address output pins. Port 2 functions change according to the operating mode. Port 2 has the following registers.
Page 267: Port 2 Data Register (P2Dr)
Section 9 I/O Ports 9.2.2 Port 2 Data Register (P2DR) P2DR stores output data for the port 2 pins. Bit Name Initial Value Description P27DR P2DR stores output data for the port 2 pins that are used as the general output port. P26DR If a port 2 read is performed while the P2DDR bits P25DR...
Page 268: Pin Functions
Section 9 I/O Ports 9.2.4 Pin Functions The relationship between register setting values and pin functions are as follows in each operating mode. In the tables, the symbol “—” stands for Don't care. Extended Mode: The function of port 2 pins is switched as shown below according to the combination of the CS256E and IOSE bits in SYSCR, the ADFULLE and CPCSE bits in BCR2 of BSC, and the P2nDDR bit.
Page 269: Port 2 Input Pull-Up Mos
Section 9 I/O Ports Single-Chip Mode: The function of port 2 pins is switched as shown below according to the combination of the OEm bit in PWOERB of PWM and the P2nDDR bit. P2nDDR — Pin function P27 to P20 input pins P27 to P20 input pins PW15 to PW8 output pins Notes: n = 7 to 0...
Page 270: Port 3 Data Direction Register (P3Ddr)
Section 9 I/O Ports 9.3.1 Port 3 Data Direction Register (P3DDR) The individual bits of P3DDR specify input or output for the pins of port 3. Bit Name Initial Value Description P37DDR In extended mode: P36DDR The port functions as the data bus regardless of the values in these bits.
Page 271: Port 3 Pull-Up Mos Control Register (P3Pcr)
Section 9 I/O Ports 9.3.3 Port 3 Pull-Up MOS Control Register (P3PCR) P3PCR controls the port 3 built-in input pull-up MOSs. Bit Name Initial Value Description P37PCR In extended mode: P36PCR Operation is not affected. In single-chip mode: P35PCR When the pins are in input state, the P34PCR corresponding input pull-up MOS is turned on P33PCR...
Page 272 Section 9 I/O Ports • P36/WUE14 The pin function is switched as shown below according to the P36DDR bit. When the WUEM14 bit in WUEMR3 of the interrupt controller is cleared to 0, this pin can be used as the WUE14 input pin. To use this pin as the WUE14 input pin, clear the P36DDR bit to 0.
Page 273 Section 9 I/O Ports • P34/WUE12/MCCMDDIR/MCCSB The pin function is switched as shown below according to the combination of the MCIF operating mode and the P34DDR bit. When the WUEM12 bit in WUEMR3 of the interrupt controller is cleared to 0, this pin can be used as the WUE12 input pin.
Page 274 Section 9 I/O Ports • P33/WUE11/MCDATDIR/MCCSA The pin function is switched as shown below according to the combination of the MCIF operating mode and the P33DDR bit. When the WUEM11 bit in WUEMR3 of the interrupt controller is cleared to 0, this pin can be used as the WUE11 input pin.
Page 275 Section 9 I/O Ports • P31/WUE9/MCCMD/MCTxD The pin function is switched as shown below according to the combination of the MCIF operating mode and the P31DDR bit. When the WUEM9 bit in WUEMR3 of the interrupt controller is cleared to 0, this pin can be used as the WUE9 input pin.
Page 276: Port 3 Input Pull-Up Mos
Section 9 I/O Ports 9.3.5 Port 3 Input Pull-Up MOS Port 3 has a built-in input pull-up MOS that can be controlled by software. This input pull-up MOS can be used in single-chip mode. Table 9.4 summarizes the input pull-up MOS states. Table 9.4 Port 3 Input Pull-Up MOS States Hardware...
Page 277: Port 4 Data Direction Register (P4Ddr)
Section 9 I/O Ports 9.4.1 Port 4 Data Direction Register (P4DDR) The individual bits of P4DDR specify input or output for the pins of port 4. Bit Name Initial Value Description P47DDR If port 4 pins are specified for use as the general I/O port, the corresponding port 4 pins are output P46DDR ports when the P4DDR bits are set to 1, and input...
Page 278: Pin Functions
Section 9 I/O Ports 9.4.3 Pin Functions The relationship between register setting values and pin functions are as follows. Note that MMC mode stands for MultiMediaCard mode, and the symbol “—” stands for Don't care in the tables. • P47/IRQ7/TMOY The pin function is switched as shown below according to the combination of the OS3 to OS0 bits in TCSR of TMR_Y and the P47DDR bit.
Page 279 Section 9 I/O Ports P45DDR Pin function P45 input pin P45 output pin TMIY (TMCIY/TMRIY) input pin/IRQ5 input pin • P44/IRQ4/TMIX/ExMCCMDDIR/ExMCCSB The pin function is switched as shown below according to the combination of the MCIF operating mode and the P44DDR bit. When the TMIXS bit in PTCNT0 is cleared to 0 and the external clock is selected by the CKS2 to CKS0 bits in TCR of TMR_X, this pin is used as the TMCIX input pin.
Page 280 Section 9 I/O Ports MCIF MCIF disable (MMCPE in IOMCR is 0) MCIF enable (MMCPE in IOMCR is 1) operating MMCS in PTCNT0 is 1 mode (Single-chip mode (EXPE = 0) MMCS in PTCNT0 is 0) Extended mode (EXPE = 1) MCIF enable (MMCPE in IOMCR is 1) MMC mode SPI mode...
Page 281 Section 9 I/O Ports • P41/IRQ1/TMI1/ExMCCMD/ExMCTxD/HSYNCI The pin function is switched as shown below according to the combination of the MCIF operating mode and the P41DDR bit. When the TMI1S bit in PTCNT0 is cleared to 0 and the external clock is selected by the CKS2 to CKS0 bits in TCR of TMR_1, this pin is used as the TMCI1 input pin.
Page 282: Port 5
Section 9 I/O Ports MCIF MCIF disable (MMCPE in IOMCR is 0) MCIF enable (MMCPE in IOMCR is 1) operating MMCS in PTCNT0 is 1 mode (Single-chip mode (EXPE = 0) MMCS in PTCNT0 is 0) Extended mode (EXPE = 1) P40DDR —...
Page 283: Port 5 Data Register (P5Dr)
Section 9 I/O Ports 9.5.2 Port 5 Data Register (P5DR) P5DR stores output data for the port 5 pins. Bit Name Initial Value Description P57DR P5DR stores output data for the port 5 pins that are used as the general output port. P56DR If a port 5 read is performed while the P5DDR bits P55DR...
Page 284 Section 9 I/O Ports • P56/IRQ14/PWX0 The pin function is switched as shown below according to the combination of the OEA bit in DACR of PWMX and the P56DDR bit. When the IRQ14E bit in IER16 of the interrupt controller is set to 1 or the ISS14 bit in ISSR16 is cleared to 0, this pin can be used as the IRQ14 input pin.
Page 285 Section 9 I/O Ports • P53/IRQ11/RxD1/IrRxD The pin function is switched as shown below according to the combination of the RE bit in SCR of SCI_1 and the P53DDR bit. When the IRQ11E bit in IER16 of the interrupt controller is set to 1 or the ISS11 bit in ISSR16 is cleared to 0, this pin can be used as the IRQ11 input pin.
Page 286: Port 6
Section 9 I/O Ports • P50/IRQ8/TxD0 The pin function is switched as shown below according to the combination of the TE bit in SCR of SCI_0 and the P50DDR bit. When the IRQ8E bit in IER16 of the interrupt controller is set to 1 or the ISS8 bit in ISSR16 is cleared to 0, this pin can be used as the IRQ8 input pin.
Page 287: Port 6 Data Direction Register (P6Ddr)
Section 9 I/O Ports 9.6.1 Port 6 Data Direction Register (P6DDR) The individual bits of P6DDR specify input or output for the pins of port 6. Bit Name Initial Value Description P67DDR Extended mode (16-bit data bus): The port functions as the data bus regardless of P66DDR the values in these bits.
Page 288: Port 6 Pull-Up Mos Control Register (Kmpcr6)
Section 9 I/O Ports 9.6.3 Port 6 Pull-Up MOS Control Register (KMPCR6) KMPCR6 controls the port 6 built-in input pull-up MOSs. Bit Name Initial Value Description KM7PCR Extended mode (16-bit data bus): Operation is not affected. KM6PCR Single-chip mode/extended mode (8-bit data bus): KM5PCR When the pins are in input state, the KM4PCR...
Page 289: System Control Register 2 (Syscr2)
Section 9 I/O Ports 9.6.4 System Control Register 2 (SYSCR2) SYSCR2 selects the port 6 input level and current specification for the input pull-up MOSs. Bit Name Initial Value Description KWUL1 Key Wakeup Level 1, 0: KWUL0 Select the port 6 input level. 00: Standard input level is selected 01: Input level 1 is selected 10: Input level 2 is selected...
Page 290: Pin Functions
Section 9 I/O Ports 9.6.5 Pin Functions The relationship between the operating modes, register setting values, and pin functions are as follows. In the tables, the symbol “—” stands for Don't care. In extended mode, port 6 pins also function as the bidirectional data bus, CompactFlash bidirectional data bus, FRT input/output pin, enhanced A/D conversion input pin, keyboard input pin, timer connection input/output pins, or I/O port.
Page 291 Section 9 I/O Ports • P66/FTOB/CIN6/KIN6/CBLANK The function of port 6 pins is switched as shown below according to the combination of the CBOE bit in TCONRO of the timer connection, the OEB bit in TOCR of FRT, and the P66DDR bit.
Page 292 Section 9 I/O Ports CLOE P64DDR — Pin function P64 input pin P64 output pin CLAMPO output pin FTIC input pin/CIN4 input pin/KIN4 input pin • P63/FTIB/CIN3/KIN3/VFBACKI The function of port 6 pins is switched as shown below according to the P63DDR bit. When the ICIBE bit in TIER of FRT is set to 1, this pin can be used as the FTIB input pin.
Page 293 Section 9 I/O Ports • P61/FTOA/CIN1/KIN1/VSYNCO The function of port 6 pins is switched as shown below according to the combination of the VOE bit in TCONRO of the timer connection, the OEA bit in TOCR of FRT, and the P61DDR bit.
Page 294 Section 9 I/O Ports Single-Chip Mode: • P67/CIN7/KIN7/DPLS The function of port 6 pins is switched as shown below according to the combination of the FADSEL bit in USBCR0 of USB and the P67DDR bit. When the KBADE bit in KBCOMP of the A/D converter is set to 1 while the KBCH2 to KBCH0 bits are set to B'111, this pin can be used as the CIN7 input pin.
Page 295 Section 9 I/O Ports • P65/FTID/CIN5/KIN5/CSYNCI/XVERDATA The function of port 6 pins is switched as shown below according to the combination of the FADSEL bit in USBCR0 of USB and the P65DDR bit. When the ICIDE bit in TIER of FRT is set to 1, this pin can be used as the FTID input pin. When the KBADE bit in KBCOMP of the A/D converter is set to 1 while the KBCH2 to KBCH0 bits are set to B'101, this pin can be used as the CIN5 input pin.
Page 296 Section 9 I/O Ports • P63/FTIB/CIN3/KIN3/VFBACKI/TXDMNS The function of port 6 pins is switched as shown below according to the combination of the FADSEL bit in USBCR0 of USB and the P63DDR bit. When the ICIBE bit in TIER of FRT is set to 1, this pin can be used as the FTIB input pin. When the KBADE bit in KBCOMP of the A/D converter is set to 1 while the KBCH2 to KBCH0 bits are set to B'011, this pin can be used as the CIN3 input pin.
Page 297 Section 9 I/O Ports • P61/FTOA/CIN1/KIN1/VSYNCO/SUSPEND The function of port 6 pins is switched as shown below according to the combination of the FADSEL bit in USBCR0 of USB, the VOE bit in TCONRO of the timer connection, the OEA bit in TOCR of FRT, and the P61DDR bit.
Page 298: Port 6 Input Pull-Up Mos
Section 9 I/O Ports 9.6.6 Port 6 Input Pull-Up MOS Port 6 has a built-in input pull-up MOS that can be controlled by software. This input pull-up MOS can be used regardless of the operating mode. Table 9.5 summarizes the input pull-up MOS states.
Page 299: Port 8
Section 9 I/O Ports Port 8 Port 8 is an 8-bit I/O port. Port 8 pins also function as the A/D converter external trigger input pin, SCI_0, SCI_1, and SCI_2 clock input/output pins, IIC_0 and IIC_1 input/output pins, ExTMR_0, ExTMR_1, ExTMR_X, and ExTMR_Y input pins, USB external clock input pin, and interrupt input pins.
Page 300: Port 8 Data Register (P8Dr)
Section 9 I/O Ports 9.8.2 Port 8 Data Register (P8DR) P8DR stores output data for the port 8 pins. Bit Name Initial Value Description P87DR P8DR stores output data for the port 8 pins that are used as the general output port. P86DR If a port 8 read is performed while the P8DDR bits P85DR...
Page 301 Section 9 I/O Ports • P86/ExIRQ14/SCK2/ExTMIX The pin function is switched as shown below according to the combination of the C/A bit in SMR of SCI_2, the CKE1 and CKE0 bits in SCR, and the P86DDR bit. When the ISS14 bit in ISSR16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ14 input pin.
Page 302 Section 9 I/O Ports • P84/ExIRQ12/SCK0/ExTMI0 The pin function is switched as shown below according to the combination of the C/A bit in SMR of SCI_0, the CKE1 and CKE0 bits in SCR, and the P84DDR bit. When the ISS12 bit in ISSR16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ12 input pin.
Page 303 Section 9 I/O Ports P82DDR — Pin function P82 input pin P82 output pin SCL1 input/output pin ExIRQ10 input pin • P81/ExIRQ9/SDA0 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of IIC_0 and the P81DDR bit. When the ISS9 bit in ISSR16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ9 input pin.
Page 304: Port 9
Section 9 I/O Ports Port 9 Port 9 is an 8-bit I/O port. However note that pin P96 cannot be used as a general output port. Port 9 pins also function as the bus control I/O pins, CompactFlash control I/O pins, the system clock output pin, and the external subclock input pin.
Page 305: Port 9 Data Register (P9Dr)
Section 9 I/O Ports 9.9.2 Port 9 Data Register (P9DR) P9DR stores output data for the port 9 pins. Bit Name Initial Value Description P97DR P9DR stores output data for the port 9 pins that are used as the general output port except for bit Undefined * P96DR P95DR...
Page 306 Section 9 I/O Ports • P96/φ/EXCL The pin function is switched as shown below according to the combination of the EXCLE bit in LPWRCR and the P96DDR bit. P96DDR EXCLE φ output pin Pin function P96 input pin EXCL input pin •...
Page 307 Section 9 I/O Ports • P92/CPCS1 The pin function is switched as shown below according to the combination of the operating mode, the CPCSE bit in BCR2 of BSC, and the P92DDR bit. Operating Extended Mode Single-Chip Mode Mode CPCSE —...
Page 308: Port A
Section 9 I/O Ports 9.10 Port A Port A is a 2-bit I/O port. Port A pins also function as the address output, keyboard input, SCI_0 and SCI_2 external control pins. Pin functions are switched depending on the operating mode. Port A has the following registers.
Page 309: Port A Input Data Register (Papin)
Section 9 I/O Ports 9.10.3 Port A Input Data Register (PAPIN) PAPIN indicates the pin states. Bit Name Initial Value Description 7 to 2 — All 1 Reserved These bits are always read as 1. Undefined * PA1PIN When a PAPIN read is performed, the pin states are always read.
Page 310 Section 9 I/O Ports • PA0/A16/KIN8/SSE0I The function of port A pins is switched as shown below according to the combination of the SSE bit in SEMR of SCI_0, the C/A bit in SMR, the CKE1 bit in SCR, the CS256E and IOSE bits in SYSCR, the ADFULLE bit in BCR2 of BSC, and the PA0DDR bit.
Page 311: Input Pull-Up Mos
Section 9 I/O Ports • PA0/KIN8/SSE0I The function of port A pins is switched as shown below according to the combination of the SSE bit in SEMR of SCI_0, the C/A bit in SMR, the CKE1 bit in SCR, and the PA0DDR bit. When the KMIM8 bit in KMIMRA of the interrupt controller is cleared to 0, this pin can be used as the KIN8 input pin.
Page 312: Change Of Peripheral Function Pins
Section 9 I/O Ports 9.11 Change of Peripheral Function Pins I/O ports that also function as peripheral modules, such as the external interrupts, 8-bit timers, and MCIF, can be changed. I/O ports that also function as the external interrupt pins are changed according to the setting of ISSR16 and ISSR.
Page 313 Section 9 I/O Ports ISSR Bit Name Initial Value Description ISS7 0: P47/IRQ7 is selected 1: P77/ExIRQ7 is selected ISS6 0: P46/IRQ6 is selected 1: P76/ExIRQ6 is selected ISS5 0: P45/IRQ5 is selected 1: P75/ExIRQ5 is selected ISS4 0: P44/IRQ4 is selected 1: P74/ExIRQ4 is selected ISS3 0: P43/IRQ3 is selected...
Page 314: Port Control Register 0 (Ptcnt0)
Section 9 I/O Ports 9.11.2 Port Control Register 0 (PTCNT0) PTCNT0 selects ports that also function as 8-bit timer input pins and MCIF I/O pins. Bit Name Initial Value Description TMI0S 0: P40/TMI0 is selected 1: P84/ExTMI0 is selected TMI1S 0: P41/TMI1 is selected 1: P85/ExTMI1 is selected TMIXS...
Page 315: Section 10 8-Bit Pwm Timer (Pwm)
Section 10 8-Bit PWM Timer (PWM) Section 10 8-Bit PWM Timer (PWM) This LSI has an on-chip pulse width modulation (PWM) timer with sixteen outputs. Sixteen output waveforms are generated from a common time base, enabling PWM output with a high carrier frequency to be produced using pulse division.
Page 316: Figure 10.1 Block Diagram Of Pwm Timer
Section 10 8-Bit PWM Timer (PWM) Figure 10.1 shows a block diagram of the PWM timer. P10/PW0 Comparator 0 PWDR0 Module P11/PW1 Comparator 1 PWDR1 data bus P12/PW2 Comparator 2 PWDR2 P13/PW3 Comparator 3 PWDR3 P14/PW4 Comparator 4 PWDR4 P15/PW5 Comparator 5 PWDR5 P16/PW6...
Page 317: Input/Output Pins
Section 10 8-Bit PWM Timer (PWM) 10.2 Input/Output Pins Table 10.1 shows the PWM output pins. Table 10.1 Pin Configuration Name Abbreviation Function PWM output 15 to 0 PW15 to PW0 Output PWM timer pulse output 15 to 0 10.3 Register Descriptions The PWM has the following registers.
Page 318: Pwm Register Select (Pwsl)
Section 10 8-Bit PWM Timer (PWM) 10.3.1 PWM Register Select (PWSL) PWSL is used to select the input clock and the PWM data register. Bit Name Initial Value Description PWCKE PWM Clock Enable PWCKS PWM Clock Select These bits, together with bits PWCKB and PWCKA in PCSR, select the internal clock input to TCNT in the PWM.
Page 319: Table 10.2 Internal Clock Selection
Section 10 8-Bit PWM Timer (PWM) Bit Name Initial Value Description Register Select These bits select the PWM data register. 0000: PWDR0 selected 0001: PWDR1 selected 0010: PWDR2 selected 0011: PWDR3 selected 0100: PWDR4 selected 0101: PWDR5 selected 0110: PWDR6 selected 0111: PWDR7 selected 1000: PWDR8 selected 1001: PWDR9 selected...
Page 320: Pwm Data Registers (Pwdr0 To Pwdr15)
Section 10 8-Bit PWM Timer (PWM) Table 10.3 Resolution, PWM Conversion Period, and Carrier Frequency when φ φ φ φ = 20 MHz Internal Clock PWM Conversion Frequency Resolution Period Carrier Frequency φ 12.8 µs 50 ns 1250 kHz φ/2 25.6 µs 100 ns 625 kHz...
Page 321: Pwm Output Enable Registers A And B (Pwoera And Pwoerb)
Section 10 8-Bit PWM Timer (PWM) PWDPRB Bit Name Initial Value Description OS15 Output Select 15 to 8 OS14 These bits select the PWM output phase. Bits OS15 to OS13 OS8 correspond to outputs PW15 to PW8. OS12 0: PWM direct output (PWDR value corresponds to high OS11 width of output) OS10...
Page 322 Section 10 8-Bit PWM Timer (PWM) PWOERB Bit Name Initial Value Description OE15 Output Enable 15 to 8 OE14 These bits, together with P2DDR, specify the P2n/PWn OE13 pin state. Bits OE15 to OE8 correspond to outputs OE12 PW15 to PW8. OE11 P2nDDR OEn: Pin state OE10...
Page 323: Peripheral Clock Select Register (Pcsr)
Section 10 8-Bit PWM Timer (PWM) 10.3.5 Peripheral Clock Select Register (PCSR) PCSR selects the PWM input clock. Bit Name Initial Value Description 7, 6 — All 0 R/(W) Reserved The initial value should not be changed. PWCKXB See section 11.3.4, Peripheral Clock Select Register PWCKXA (PCSR).
Page 324: Operation
Section 10 8-Bit PWM Timer (PWM) 10.4 Operation The upper four bits of PWDR specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16. Table 10.4 shows the duty cycles of the basic pulse. Table 10.4 Duty Cycle of Basic Pulse Upper 4 Bits Basic Pulse Waveform (Internal)
Page 325: Figure 10.2 Example Of Additional Pulse Timing (When Upper 4 Bits Of Pwdr = B'1000)
Section 10 8-Bit PWM Timer (PWM) The lower four bits of PWDR specify the position of pulses added to the 16 basic pulses. An additional pulse adds a high period (when OS = 0) with a width equal to the resolution before the rising edge of a basic pulse.
Page 326 Section 10 8-Bit PWM Timer (PWM) Rev. 3.00 Jan 25, 2006 page 272 of 872 REJ09B0286-0300...
Page 327: Section 11 14-Bit Pwm Timer (Pwmx)
Section 11 14-Bit PWM Timer (PWMX) Section 11 14-Bit PWM Timer (PWMX) This LSI has an on-chip 14-bit pulse-width modulator (PWM) timer with two output channels. It can be connected to an external low-pass filter to operate as a 14-bit D/A converter. 11.1 Features •...
Page 328: Input/Output Pins
Section 11 14-Bit PWM Timer (PWMX) 11.2 Input/Output Pins Table 11.1 lists the PWM (D/A) module input and output pins. Table 11.1 Pin Configuration Name Abbreviation Function PWM output pin X0 PWX0 Output PWM output of PWMX channel A PWM output pin X1 PWX1 Output PWM output of PWMX channel B...
Page 329: Pwm D/A Counter H, L (Dacnth, Dacntl)
Section 11 14-Bit PWM Timer (PWMX) 11.3.1 PWM D/A Counter H, L (DACNTH, DACNTL) DACNT is a 14-bit readable/writable up-counter. The input clock is selected by the clock select bit (CKS) in DACR. DACNT functions as the time base for both PWM (D/A) channels. When a channel operates with 14-bit precision, it uses all DACNT bits.
Page 330: Pwm (D/A) Data Registers A And B (Dadra And Dadrb)
Section 11 14-Bit PWM Timer (PWMX) 11.3.2 PWM (D/A) Data Registers A and B (DADRA and DADRB) DADRA corresponds to PWM (D/A) channel A, and DADRB to PWM (D/A) channel B. The DADR registers cannot be accessed in 8-bit units. The DADR registers should always be accessed in 16-bit units.
Page 331: Pwm (D/A) Control Register (Dacr)
Section 11 14-Bit PWM Timer (PWMX) DADRB Bit Name Initial Value Description DA13 D/A Data 13 to 0 DA12 These bits set a digital value to be converted to an DA11 analog value. DA10 In each base cycle, the DACNT value is continually compared with the DADR value to determine the duty cycle of the output waveform, and to decide whether to output a fine-adjustment pulse equal in width to the...
Page 332 Section 11 14-Bit PWM Timer (PWMX) Bit Name Initial Value Description — R/(W) Reserved The initial value should not be changed. PWME PWM Enable Starts or stops the PWM D/A counter (DACNT). 0: DACNT operates as a 14-bit up-counter 1: DACNT halts at H'0003 5, 4 —...
Page 333: Peripheral Clock Select Register (Pcsr)
Section 11 14-Bit PWM Timer (PWMX) 11.3.4 Peripheral Clock Select Register (PCSR) PCSR selects the operating speed of DACR. Bit Name Initial Value Description 7, 6 — All 0 R/(W) Reserved The initial value should not be changed. PWCKXB PWMX Clock Select PWCKXA Select the clock when the CKS bit in DACR of PWMX is set to 1.
Page 334: Bus Master Interface
Section 11 14-Bit PWM Timer (PWMX) 11.4 Bus Master Interface DACNT, DADRA, and DADRB are 16-bit registers. The data bus linking the bus master and the on-chip peripheral modules, however, is only 8 bits wide. When the bus master accesses these registers, it therefore uses an 8-bit temporary register (TEMP).
Page 335: Operation
Section 11 14-Bit PWM Timer (PWMX) 11.5 Operation A PWM waveform like the one shown in figure 11.2 is output from the PWMX pin. The value in DADR corresponds to the total width (T ) of the low (0) pulses output in one conversion cycle (256 pulses when CFS = 0, 64 pulses when CFS = 1).
Page 336: Table 11.3 Settings And Operation (Examples When Φ = 25 Mhz)
Section 11 14-Bit PWM Timer (PWMX) Table 11.3 Settings and Operation (Examples when φ φ φ φ = 25 MHz) PCSR Fixed DADR Bits Base Cycle Conversion Conversion Resolution TL/TH Conversion Bit Data Cycle * (µs)/ Cycle (µs)/ T (µs) (OS = 0/OS = 1) PWCKXB PWCKXA Accuracy...
Page 337: Figure 11.3 Output Waveform (Os = 0, Dadr Corresponds To T L )
Section 11 14-Bit PWM Timer (PWMX) 1 conversion cycle f255 f256 L255 L256 = ··· = t = T× 64 f255 f256 + ··· + t L255 L256 a. CFS = 0 [base cycle = resolution (T) × 64] 1 conversion cycle = ···...
Page 338: Figure 11.4 Output Waveform (Os = 1, Dadr Corresponds To T H )
Section 11 14-Bit PWM Timer (PWMX) 1 conversion cycle f255 f256 H255 H256 = ··· = t = T× 64 f255 f256 + ··· + t H255 H256 a. CFS = 0 [base cycle = resolution (T) × 64] 1 conversion cycle = ···...
Page 339: Figure 11.6 Output Waveform When Dadr = H'0207 (Os = 1)
Section 11 14-Bit PWM Timer (PWMX) In this example, DADR = H'0207 (B'0000 0010 0000 0111). The output waveform is shown in figure 11.6. Since CFS = 1 and the value of the upper eight bits is B'0000 0010, the high width of the base pulse duty cycle is 2/256 ×...
Page 340: Table 11.4 Locations Of Additional Pulses Added To Base Pulse (When Cfs = 1)
Section 11 14-Bit PWM Timer (PWMX) Table 11.4 Locations of Additional Pulses Added to Base Pulse (When CFS = 1) Rev. 3.00 Jan 25, 2006 page 286 of 872 REJ09B0286-0300...
Page 341: Section 12 16-Bit Free-Running Timer (Frt)
Section 12 16-Bit Free-Running Timer (FRT) Section 12 16-Bit Free-Running Timer (FRT) This LSI has an on-chip 16-bit free-running timer (FRT). The FRT operates on the basis of the 16- bit free-running counter (FRC), and outputs two independent waveforms, and measures the input pulse width and external clock periods.
Page 342: Figure 12.1 Block Diagram Of 16-Bit Free-Running Timer
Section 12 16-Bit Free-Running Timer (FRT) External clock Internal clock OCRAR/F (H/L) φ/2 φ/8 φ/32 FTCI Clock Clock selector OCRA (H/L) Compare-match A Comparator A FTOA Internal data bus Overflow FTOB FRC (H/L) Clear FTIA Compare-match B Comparator B Control logic FTIB FTIC OCRB (H/L)
Page 343: Input/Output Pins
Section 12 16-Bit Free-Running Timer (FRT) 12.2 Input/Output Pins Table 12.1 lists the FRT input and output pins. Table 12.1 Pin Configuration Name Abbreviation Function Counter clock input pin FTCI Input FRC counter clock input Output compare A output pin FTOA Output Output compare A output...
Page 344: Free-Running Counter (Frc)
Section 12 16-Bit Free-Running Timer (FRT) 12.3.1 Free-Running Counter (FRC) FRC is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS1 and CKS0 in TCR. FRC can be cleared by compare-match A. When FRC overflows from H'FFFF to H'0000, the overflow flag bit (OVF) in TCSR is set to 1.
Page 345: Output Compare Registers Ar And Af (Ocrar And Ocraf)
Section 12 16-Bit Free-Running Timer (FRT) 12.3.4 Output Compare Registers AR and AF (OCRAR and OCRAF) OCRAR and OCRAF are 16-bit readable/writable registers. When the OCRAMS bit in TOCR is set to 1, the operation of OCRA is changed to include the use of OCRAR and OCRAF. The contents of OCRAR and OCRAF are automatically added alternately to OCRA, and the result is written to OCRA.
Page 346: Timer Interrupt Enable Register (Tier)
Section 12 16-Bit Free-Running Timer (FRT) 12.3.6 Timer Interrupt Enable Register (TIER) TIER enables and disables interrupt requests. Bit Name Initial Value Description ICIAE Input Capture Interrupt A Enable Selects whether to enable input capture interrupt A request (ICIA) when input capture flag A (ICFA) in TCSR is set to 1.
Page 347: Timer Control/Status Register (Tcsr)
Section 12 16-Bit Free-Running Timer (FRT) Bit Name Initial Value Description OCIBE Output Compare Interrupt B Enable Selects whether to enable output compare interrupt B request (OCIB) when output compare flag B (OCFB) in TCSR is set to 1. 0: OCIB requested by OCFB is disabled 1: OCIB requested by OCFB is enabled OVIE Timer Overflow Interrupt Enable...
Page 348 Section 12 16-Bit Free-Running Timer (FRT) Bit Name Initial Value Description R/(W) * Input Capture Flag B ICFB This status flag indicates that the FRC value has been transferred to ICRB by means of an input capture signal. When BUFEB = 1, ICFB indicates that the old ICRB value has been moved into ICRD and the new FRC value has been transferred to ICRB.
Page 349 Section 12 16-Bit Free-Running Timer (FRT) Bit Name Initial Value Description R/(W) * Output Compare Flag A OCFA This status flag indicates that the FRC value matches the OCRA value. [Setting condition] When FRC = OCRA [Clearing condition] Read OCFA when OCFA = 1, then write 0 to OCFA R/(W) * Output Compare Flag B OCFB This status flag indicates that the FRC value matches...
Page 350: Timer Control Register (Tcr)
Section 12 16-Bit Free-Running Timer (FRT) 12.3.8 Timer Control Register (TCR) TCR selects the rising or falling edge of the input capture signals, enables the input capture buffer mode, and selects the FRC clock source. Bit Name Initial Value Description IEDGA Input Edge Select A Selects the rising or falling edge of the input capture A...
Page 351: Timer Output Compare Control Register (Tocr)
Section 12 16-Bit Free-Running Timer (FRT) Bit Name Initial Value Description CKS1 Clock Select 1, 0 CKS0 Select clock source for FRC. 00: φ/2 internal clock source 01: φ/8 internal clock source 10: φ/32 internal clock source 11: External clock source (counting at FTCI rising edge) 12.3.9 Timer Output Compare Control Register (TOCR) TOCR enables output from the output compare pins, selects the output levels, switches access...
Page 352 Section 12 16-Bit Free-Running Timer (FRT) Bit Name Initial Value Description OCRS Output Compare Register Select OCRA and OCRB share the same address. When this address is accessed, the OCRS bit selects which register is accessed. The operation of OCRA or OCRB is not affected.
Page 353: Operation
Section 12 16-Bit Free-Running Timer (FRT) 12.4 Operation 12.4.1 Pulse Output Figure 12.2 shows an example of 50%-duty pulses output with an arbitrary phase difference. When a compare match occurs while the CCLRA bit in TCSR is set to 1, the OLVLA and OLVLB bits are inverted by software.
Page 354: Operation Timing
Section 12 16-Bit Free-Running Timer (FRT) 12.5 Operation Timing 12.5.1 FRC Increment Timing Figure 12.3 shows the FRC increment timing with an internal clock source. Figure 12.4 shows the increment timing with an external clock source. The pulse width of the external clock signal must be at least 1.5 system clocks (φ).
Page 355: Output Compare Output Timing
Section 12 16-Bit Free-Running Timer (FRT) 12.5.2 Output Compare Output Timing A compare-match signal occurs at the last state when the FRC and OCR values match (at the timing when the FRC updates the counter value). When a compare-match signal occurs, the level selected by the OLVL bit in TOCR is output at the output compare pin (FTOA or FTOB).
Page 356: Input Capture Input Timing
Section 12 16-Bit Free-Running Timer (FRT) 12.5.4 Input Capture Input Timing The rising or falling edge can be selected for the input capture input timing by the IEDGA to IEDGD bits in TCR. Figure 12.7 shows the usual input capture timing when the rising edge is selected.
Page 357: Buffered Input Capture Input Timing
Section 12 16-Bit Free-Running Timer (FRT) 12.5.5 Buffered Input Capture Input Timing ICRC and ICRD can operate as buffers for ICRA and ICRB, respectively. Figure 12.9 shows how input capture operates when ICRC is used as ICRA's buffer register (BUFEA = 1) and IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDGA = 1 and IEDGC = 0), so that input capture is performed on both the rising and falling edges of FTIA.
Page 358: Timing Of Input Capture Flag (Icf) Setting
Section 12 16-Bit Free-Running Timer (FRT) CPU read cycle of ICRA or ICRC φ FTIA Input capture signal Figure 12.10 Buffered Input Capture Timing (BUFEA = 1) 12.5.6 Timing of Input Capture Flag (ICF) Setting The input capture flag, ICFA, ICFB, ICFC, or ICFD, is set to 1 by the input capture signal. The FRC value is simultaneously transferred to the corresponding input capture register (ICRA, ICRB, ICRC, or ICRD).
Page 359: Timing Of Output Compare Flag (Ocf) Setting
Section 12 16-Bit Free-Running Timer (FRT) 12.5.7 Timing of Output Compare Flag (OCF) setting The output compare flag, OCFA or OCFB, is set to 1 by a compare-match signal generated when the FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the last state in which the two values match, just before FRC increments to a new value.
Page 360: Automatic Addition Timing
Section 12 16-Bit Free-Running Timer (FRT) φ H'FFFF H'0000 Overflow signal Figure 12.13 Timing of Overflow Flag (OVF) Setting 12.5.9 Automatic Addition Timing When the OCRAMS bit in TOCR is set to 1, the contents of OCRAR and OCRAF are automatically added to OCRA alternately, and when an OCRA compare-match occurs a write to OCRA is performed.
Page 361: 12.5.10 Mask Signal Generation Timing
Section 12 16-Bit Free-Running Timer (FRT) 12.5.10 Mask Signal Generation Timing When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000, a signal that masks the ICRD input capture signal is generated. The mask signal is set by the input capture signal.
Page 362: Interrupt Sources
Section 12 16-Bit Free-Running Timer (FRT) 12.6 Interrupt Sources The free-running timer can request seven interrupts: ICIA to ICID, OCIA, OCIB, and FOVI. Each interrupt can be enabled or disabled by an enable bit in TIER. Independent signals are sent to the interrupt controller for each interrupt.
Page 363: Usage Notes
Section 12 16-Bit Free-Running Timer (FRT) 12.7 Usage Notes 12.7.1 Conflict between FRC Write and Clear If an internal counter clear signal is generated during the state after an FRC write cycle, the clear signal takes priority and the write is not performed. Figure 12.17 shows the timing for this type of conflict.
Page 364: Conflict Between Frc Write And Increment
Section 12 16-Bit Free-Running Timer (FRT) 12.7.2 Conflict between FRC Write and Increment If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes priority and FRC is not incremented. Figure 12.18 shows the timing for this type of conflict. Write cycle of FRC φ...
Page 365: Conflict Between Ocr Write And Compare-Match
Section 12 16-Bit Free-Running Timer (FRT) 12.7.3 Conflict between OCR Write and Compare-Match If a compare-match occurs during the state after an OCRA or OCRB write cycle, the write takes priority and the compare-match signal is disabled. Figure 12.19 shows the timing for this type of conflict.
Page 366: Switching Of Internal Clock And Frc Operation
Section 12 16-Bit Free-Running Timer (FRT) φ OCRAR (OCRAF) Address address Internal write signal Old data New data OCRAR (OCRAF) Disabled Compare-match signal Automatic addition is not performed because compare-match signals are disabled. Figure 12.20 Conflict between OCR Write and Compare-Match (When Automatic Addition Function Is Used) 12.7.4 Switching of Internal Clock and FRC Operation...
Page 367: Table 12.3 Switching Of Internal Clock And Frc Operation
Section 12 16-Bit Free-Running Timer (FRT) Table 12.3 Switching of Internal Clock and FRC Operation Timing of Switchover by Means of CKS1 and CKS0 Bits FRC Operation Switching from Clock before low to low switchover Clock after switchover FRC clock N + 1 CKS bit rewrite Switching from...
Page 368 Section 12 16-Bit Free-Running Timer (FRT) Timing of Switchover by Means of CKS1 and CKS0 Bits FRC Operation Switching from Clock before high to high switchover Clock after switchover FRC clock N + 1 N + 2 CKS bit rewrite Note: * Generated on the assumption that the switchover is a falling edge;...
Page 369: Section 13 8-Bit Timer (Tmr)
Section 13 8-Bit Timer (TMR) Section 13 8-Bit Timer (TMR) This LSI has an on-chip 8-bit timer module (TMR_0 and TMR_1) with two channels operating on the basis of an 8-bit counter. The 8-bit timer module can be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers.
Page 370 Section 13 8-Bit Timer (TMR) An input capture function is added to TMR_X. For details, see section 14, Timer Connection. External clock Internal clock TMR_0 TMR_1 φ/2, φ/8 φ/2, φ/8 TMCI0 φ/32, φ/64 φ/64, φ/128 TMCI1 φ/256, φ/1024 φ/1024, φ/2048 Clock 1 Clock 0 Select clock...
Page 371: Figure 13.2 Block Diagram Of 8-Bit Timer (Tmr_Y And Tmr_X)
Section 13 8-Bit Timer (TMR) External clock Internal clock TMR_Y TMR_X φ/4 φ TMCIY φ/256 φ/2 TMCIX φ/2048 φ/4 Clock X Clock Y Select clock TCORA_Y TCORA_X Compare match AX Comparator A_Y Comparator A_X Compare match AY Overflow X Overflow Y TCNT_Y TCNT_X Clear Y...
Page 372: Input/Output Pins
Section 13 8-Bit Timer (TMR) 13.2 Input/Output Pins Table 13.1 summarizes the input and output pins of the TMR. Table 13.1 Pin Configuration Channel Name Symbol Function TMR_0 Timer output TMO0 Output Output controlled by compare-match Timer clock/reset TMI0/ExTMI0 Input External clock input (TMCI0)/external input reset input (TMRI0) for the counter...
Page 373 Section 13 8-Bit Timer (TMR) TMR_1 • Timer counter_1 (TCNT_1) • Time constant register A_1 (TCORA_1) • Time constant register B_1 (TCORB_1) • Timer control register_1 (TCR_1) • Timer control/status register_1 (TCSR_1) TMR_Y • Timer counter_Y (TCNT_Y) • Time constant register A_Y (TCORA_Y) •...
Page 374: Timer Counter (Tcnt)
Section 13 8-Bit Timer (TMR) 13.3.1 Timer Counter (TCNT) Each TCNT is an 8-bit readable/writable up-counter. TCNT_0 and TCNT_1 (or TCNT_Y and TCNT_X) comprise a single 16-bit register, so they can be accessed together by word access. The clock source is selected by the CKS2 to CKS0 bits in TCR. TCNT can be cleared by an external reset input signal, compare-match A signal or compare-match B signal.
Page 375: Timer Control Register (Tcr)
Section 13 8-Bit Timer (TMR) 13.3.4 Timer Control Register (TCR) TCR selects the TCNT clock source and the condition by which TCNT is cleared, and enables/disables interrupt requests. Bit Name Initial Value R/W Description CMIEB Compare-Match Interrupt Enable B Selects whether the CMFB interrupt request (CMIB) is enabled or disabled when the CMFB flag in TCSR is set to 1.
Page 376: Table 13.2 Clock Input To Tcnt And Count Condition
Section 13 8-Bit Timer (TMR) Table 13.2 Clock Input to TCNT and Count Condition STCR Channel Description CKS2 CKS1 CKS0 ICKS1 ICKS0 TMR_0 — — Disables clock input Increments at falling edge of internal clock φ/8 — Increments at falling edge of internal clock φ/2 —...
Page 377: Timer Control/Status Register (Tcsr)
Section 13 8-Bit Timer (TMR) 13.3.5 Timer Control/Status Register (TCSR) TCSR indicates the status flags and controls compare-match output. TCSR_0 Bit Name Initial Value R/W Description R/(W) * Compare-Match Flag B CMFB [Setting condition] • When the values of TCNT_0 and TCORB_0 match [Clearing condition] •...
Page 378 Section 13 8-Bit Timer (TMR) Bit Name Initial Value R/W Description Output Select 3, 2 These bits specify how the TMO0 pin output level is to be changed by compare-match B of TCORB_0 and TCNT_0. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Output Select 1, 0...
Page 379 Section 13 8-Bit Timer (TMR) Bit Name Initial Value Description R/(W) * Timer Overflow Flag [Setting condition] • When TCNT_1 overflows from H'FF to H'00 [Clearing condition] • Read OVF when OVF = 1, then write 0 in OVF — Reserved This bit is always read as 1 and cannot be modified.
Page 380 Section 13 8-Bit Timer (TMR) TCSR_X Bit Name Initial Value Description R/(W) * Compare-Match Flag B CMFB [Setting condition] • When the values of TCNT_X and TCORB_X match [Clearing condition] • Read CMFB when CMFB = 1, then write 0 in CMFB R/(W) * Compare-Match Flag A CMFA [Setting condition]...
Page 381 Section 13 8-Bit Timer (TMR) Bit Name Initial Value Description Output Select 1, 0 These bits specify how the TMOX pin output level is to be changed by compare-match A of TCORA_X and TCNT_X. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Note:...
Page 382: Input Capture Register (Ticr)
Section 13 8-Bit Timer (TMR) Bit Name Initial Value Description Output Select 3, 2 These bits specify how the TMOY pin output level is to be changed by compare-match B of TCORB_Y and TCNT_Y. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Output Select 1, 0...
Page 383: Input Capture Registers R And F (Ticrr And Ticrf)
Section 13 8-Bit Timer (TMR) 13.3.8 Input Capture Registers R and F (TICRR and TICRF) TICRR and TICRF are 8-bit read-only registers. The contents of TCNT are transferred at the rising edge and falling edge of the external reset input in that order, when the ICST bit in TCONRI of the timer connection is set to 1.
Page 384: Operation
Section 13 8-Bit Timer (TMR) 13.4 Operation 13.4.1 Pulse Output Figure 13.3 shows an example for outputting an arbitrary duty pulse. 1. Clear the CCLR1 bit in TCR to 0 so that TCNT is cleared according to the compare match of TCORA, and then set the CCLR0 bit to 1.
Page 385: Operation Timing
Section 13 8-Bit Timer (TMR) 13.5 Operation Timing 13.5.1 TCNT Count Timing Figure 13.4 shows the TCNT count timing with an internal clock source. Figure 13.5 shows the TCNT count timing with an external clock source. The pulse width of the external clock signal must be at least 1.5 system clocks (φ) for a single edge and at least 2.5 system clocks (φ) for both edges.
Page 386: Timing Of Cmfa And Cmfb Setting At Compare-Match
Section 13 8-Bit Timer (TMR) 13.5.2 Timing of CMFA and CMFB Setting at Compare-Match The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the TCNT and TCOR values match. The compare-match signal is generated at the last state in which the match is true, just when the timer counter is updated.
Page 387: Timing Of Counter Clear At Compare-Match
Section 13 8-Bit Timer (TMR) 13.5.4 Timing of Counter Clear at Compare-Match TCNT is cleared when compare-match A or compare-match B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 13.8 shows the timing of clearing the counter by a compare-match.
Page 388: Timing Of Overflow Flag (Ovf) Setting
Section 13 8-Bit Timer (TMR) 13.5.6 Timing of Overflow Flag (OVF) Setting The OVF bit in TCSR is set to 1 when the TCNT overflows (changes from H'FF to H'00). Figure 13.10 shows the timing of OVF flag setting. φ TCNT H'FF H'00...
Page 389: Tmr_0 And Tmr_1 Cascaded Connection
Section 13 8-Bit Timer (TMR) 13.6 TMR_0 and TMR_1 Cascaded Connection If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer can be used (16-bit count mode) or the compare-matches of the 8-bit timer of channel 0 can be counted by the 8-bit timer of channel 1 (compare-match count mode).
Page 390: Input Capture Operation
Section 13 8-Bit Timer (TMR) 13.7 Input Capture Operation TMR_X has input capture registers (TICR, TICRR and TICRF). A narrow pulse width can be measured with TICRR and TICRF, using a single capture operation controlled by the ICST bit in TCONRI of the timer connection.
Page 391: Figure 13.12 Timing Of Input Capture Signal (Input Capture Signal Is Input During Ticrr And Ticrf Read)
Section 13 8-Bit Timer (TMR) TICRR, TICRF read cycle φ TMRIX Input capture signal Figure 13.12 Timing of Input Capture Signal (Input Capture Signal Is Input during TICRR and TICRF Read) Selection of Input Capture Signal Input: TMRIX (input capture input signal of TMR_X) is switched according to the setting of the bits in TCONRI of the timer connection.
Page 392: Interrupt Sources
Section 13 8-Bit Timer (TMR) Table 13.3 Input Capture Signal Selection TCONRI Bit 4 Bit 7 Bit 6 Bit 3 Bit 1 ICST SIMOD1 SIMOD0 HFINV HIINV Description — — — — Input capture function not used — TMIX pin input selection —...
Page 393: Usage Notes
Section 13 8-Bit Timer (TMR) Table 13.4 Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y, and TMR_X Interrupt Interrupt Channel Name Interrupt Source Flag Activation Priority TMR_X CMIAX TCORA_X compare-match CMFA Possible High CMIBX TCORB_X compare-match CMFB Possible OVIX TCNT_X overflow Not possible ICIX Input capture...
Page 394: Conflict Between Tcnt Write And Increment
Section 13 8-Bit Timer (TMR) TCNT write cycle by CPU φ Address TCNT address Internal write signal Counter clear signal TCNT H'00 Figure 13.14 Conflict between TCNT Write and Clear 13.9.2 Conflict between TCNT Write and Increment If a TCNT input clock is generated during the T2 state of a TCNT write cycle as shown in figure 13.15, the write takes priority and the counter is not incremented.
Page 395: Conflict Between Tcor Write And Compare-Match
Section 13 8-Bit Timer (TMR) 13.9.3 Conflict between TCOR Write and Compare-Match If a compare-match occurs during the T2 state of a TCOR write cycle as shown in figure 13.16, the TCOR write takes priority and the compare-match signal is disabled. With TMR_X, a TICR input capture conflicts with a compare-match in the same way as with a write to TCORC.
Page 396: Conflict Between Compare-Matches A And B
Section 13 8-Bit Timer (TMR) 13.9.4 Conflict between Compare-Matches A and B If compare-matches A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output states set for compare-match A and compare-match B, as shown in table 13.5.
Page 397: Table 13.6 Switching Of Internal Clocks And Tcnt Operation
Section 13 8-Bit Timer (TMR) Table 13.6 Switching of Internal Clocks and TCNT Operation Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Clock switching from low Clock before to low level * switchover Clock after switchover TCNT clock...
Page 398: Mode Setting With Cascaded Connection
Section 13 8-Bit Timer (TMR) Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Clock switching from Clock before switchover high to high level Clock after switchover TCNT clock TCNT N + 1 N + 2 CKS bit rewrite Notes: 1.
Page 399: Section 14 Timer Connection
Section 14 Timer Connection Section 14 Timer Connection This LSI allows interconnection between a 16-bit free-running timer (FRT) and three 8-bit timer channels (TMR_1, TMR_X, and TMR_Y). This capability can be used to implement complex functions such as PWM decoding and clamp waveform output. 14.1 Features •...
Page 400: Figure 14.1 Block Diagram Of Timer Connection
Section 14 Timer Connection Edge detection Phase Read VSYNCI/ flag FTIA inversion IVI signal Edge detection Phase VFBACKI/ signal Phase signal inversion VSYNC FTIB selection inversion sync selection modify output selection VSYNCO/ 16-bit FRT FTIA FTOA FTOA IVG signal IVO signal FTIB CMA(R) input...
Page 401: Input/Output Pins
Section 14 Timer Connection 14.2 Input/Output Pins Table 14.1 lists the timer connection input and output pins. Table 14.1 Pin Configuration Input/ Name Abbreviation Output Function Vertical synchronization signal VSYNCI Input Vertical synchronization signal input pin input pin or FTIA input pin Horizontal synchronization signal HSYNCI Input...
Page 402: Timer Connection Register I (Tconri)
Section 14 Timer Connection 14.3.1 Timer Connection Register I (TCONRI) TCONRI controls connection between timers, the signal source for synchronization signal input, phase inversion, etc. Bit Name Initial Value Description SIMOD1 Input Synchronization Mode Select 1, 0 SIMOD0 These bits select the signal source of the IHI and IVI signals.
Page 403 Section 14 Timer Connection Bit Name Initial Value Description ICST Input Capture Start Bit The TMR_X external reset input (TMRIX) is connected to the IHI signal. TMR_X has input capture registers (TICR, TICRR, and TICRF). TICRR and TICRF can measure the width of a pulse by means of a single capture operation under the control of the ICST bit.
Page 404 Section 14 Timer Connection Bit Name Initial Value Description HFINV Input Synchronization Signal Inversion VFINV These bits select inversion of the input phase of the spare horizontal synchronization signal (HFBACKI), HIINV the spare vertical synchronization signal (VFBACKI), VIINV the horizontal synchronization signal (HSYNCI), composite synchronization signal (CSYNCI), and the vertical synchronization signal (VSYNCI).
Page 405: Table 14.2 Synchronization Signal Connection Enable
Section 14 Timer Connection Table 14.2 Synchronization Signal Connection Enable Bit 5 Description SCONE Mode FTIA FTIB FTIC FTID TMCI1 TMRI1 Normal connection (Initial value) FTIA FTIB FTIC FTID TMI1 TMI1 input input input input input input Synchronization signal TMO1 VFBACKI connection mode signal...
Page 406: Timer Connection Register O (Tconro)
Section 14 Timer Connection 14.3.2 Timer Connection Register O (TCONRO) TCONRO controls output signal output, phase inversion, etc. Bit Name Initial Value Description Output Enable These bits control enabling/disabling of output of horizontal synchronization signal (HSYNCO), CLOE vertical synchronization signal (VSYNCO), clamp CBOE waveform (CLAMPO), and blanking waveform (CBLANK) output.
Page 407 Section 14 Timer Connection Bit Name Initial Value Description HOINV Output Synchronization Signal Inversion VOINV These bits select inversion of the output phase of the horizontal synchronization signal (HSYNCO), the CLOINV vertical synchronization signal (VSYNCO), the CBOINV clamp waveform (CLAMPO), and the blanking waveform (CBLANK).
Page 408: Timer Connection Register S (Tconrs)
Section 14 Timer Connection 14.3.3 Timer Connection Register S (TCONRS) TCONRS selects whether to access TMR_X or TMR_Y registers, and the synchronization signal output signal source and generation method. Bit Name Initial Value Description TMR_X/Y TMR_X/TMR_Y Access Select For details, see table 14.3. 0: The TMR_X registers are accessed at addresses H'(FF)FFF0 to H'(FF)FFF5 1: The TMR_Y registers are accessed at addresses...
Page 409: Table 14.3 Registers Accessible By Tmr_X/Tmr_Y
Section 14 Timer Connection Bit Name Initial Value Description VOMOD1 Vertical Synchronization Output Mode Select 1, 0 VOMOD0 These bits select the signal source and generation method for the IVO signal. • ISGENE = 0 00: The IVI signal (without fall modification or IHI synchronization) is selected 01: The IVI signal (without fall modification, with IHI synchronization) is selected...
Page 410: Edge Sense Register (Sedgr)
Section 14 Timer Connection 14.3.4 Edge Sense Register (SEDGR) SEDGR detects a rising edge on the timer connection input pins and the occurrence of 2fH modification, and determines the phase of the IVI and IHI signals. Bit Name Initial Value Description R/(W) * VEDG...
Page 411 Section 14 Timer Connection Bit Name Initial Value Description R/(W) * VFEDG VFBACKI Edge Detects a rising edge on the VFBACKI pin. [Clearing condition] When 0 is written in VFEDG after reading VFEDG = 1 [Setting condition] When a rising edge is detected on the VFBACKI pin R/(W) * PREDG Pre-Equalization Flag...
Page 412: Operation
Section 14 Timer Connection 14.4 Operation 14.4.1 PWM Decoding (PDC Signal Generation) The timer connection facility and TMR_X can be used to decode a PWM signal in which 0 and 1 are represented by the pulse width. To do this, a signal in which a rising edge is generated at regular intervals must be selected as the IHI signal.
Page 413: Clamp Waveform Generation (Cl1/Cl2/Cl3 Signal Generation)
Section 14 Timer Connection IHI signal is tested at compare-match IHI signal PDC signal TCNT TCORB (threshold) Counter clear At the 2nd compare-match, Counter reset caused by IHI signal is not tested caused by TCNT overflow IHI signal Figure 14.2 Timing Chart for PWM Decoding 14.4.2 Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation) The timer connection facility and TMR_X can be used to generate signals with different duty...
Page 414: Figure 14.3 Timing Chart For Clamp Waveform Generation (Cl1 And Cl2 Signals)
Section 14 Timer Connection contents of TICR and TCORC. Caution is required if the rising edge of the IHI signal precedes the fall timing set by the contents of TCORC, since the IHI signal will cause the CL3 signal to fall. Examples of TCR settings of TMR_X are the same as those in table 14.4.
Page 415: 8-Bit Timer Divided Waveform Period Measurement
Section 14 Timer Connection 14.4.3 8-Bit Timer Divided Waveform Period Measurement The timer connection facility, TMR_1, and the free-running timer (FRT) can be used to measure the period of an IHI signal divided waveform. Since TMR_1 can be cleared by a rising edge of the inverted IVI signal, the rise and fall of the IHI signal divided waveform can be synchronized with the IVI signal.
Page 416: Table 14.6 Examples Of Tcr And Tcsr Settings
Section 14 Timer Connection Table 14.6 Examples of TCR and TCSR Settings Register Abbreviation Contents Description TCR in TMR_1 CMIEB Interrupts due to compare-match and overflow are disabled CMIEA OVIE 4, 3 CCLR1, CCLR0 TCNT is cleared by the rising edge of the external reset signal (inverse of the IVI signal) 2 to 0...
Page 417: Ihi Signal And 2Fh Modification
Section 14 Timer Connection IVI signal IHI signal divided waveform ICRB(4) ICRB(3) ICRB(2) ICRB(1) ICRB Figure 14.5 Timing Chart for Measurement of IVI Signal and IHI Signal Divided Waveform Periods 14.4.4 IHI Signal and 2fH Modification By using the timer connection facility and FRT, even if there is a part of the IHI signal with twice the frequency, this can be eliminated.
Page 418: Figure 14.6 2Fh Modification Timing Chart
Section 14 Timer Connection Table 14.7 Examples of TCR, TCSR, TOCR, and OCRDM Settings Register Abbreviation Contents Description TCR in FRT IEDGD FRC value is transferred to ICRD on the rising edge of input capture input D (IHI signal) 1, 0 CKS1, CKS0 FRC is incremented on internal clock: φ/8...
Page 419: Ivi Signal Fall Modification And Ihi Synchronization
Section 14 Timer Connection 14.4.5 IVI Signal Fall Modification and IHI Synchronization By using the timer connection facility and TMR_1, the fall of the IVI signal can be shifted backward by the specified number of IHI signal waveforms. Also, the fall of the IVI signal can be synchronized with the rise of the IHI signal.
Page 420: Figure 14.7 Fall Modification And Ihi Synchronization Timing Chart
Section 14 Timer Connection Table 14.8 Examples of TCR, TCSR, and TCORB Settings Register Abbreviation Contents Description TCR in CMIEB Interrupts due to compare-match and TMR_1 overflow are disabled CMIEA OVIE 4, 3 CCLR1, TCNT is cleared by the rising edge of the CCLR0 external reset signal (inverse of the IVI signal)
Page 421: Internal Synchronization Signal Generation (Ihg/Ivg/Cl4 Signal Generation)
Section 14 Timer Connection 14.4.6 Internal Synchronization Signal Generation (IHG/IVG/CL4 Signal Generation) By using the timer connection facility, FRT, and TMR_Y, it is possible to automatically generate internal signals (IHG and IVG signals) corresponding to the IHI and IVI signals. As the IHG signal is synchronized with the rise of the IVG signal, the IHG signal period must be made a divisor of the IVG signal period in order to keep it constant.
Page 422: Table 14.9 Examples Of Tcr, Tcsr, Tcora, Tcorb, Ocrar, Ocraf, And Tocr Settings
Section 14 Timer Connection Table 14.9 Examples of TCR, TCSR, TCORA, TCORB, OCRAR, OCRAF, and TOCR Settings Register Abbreviation Contents Description TCR in CMIEB Interrupts due to compare-match and TMR_Y overflow are disabled CMIEA OVIE 4, 3 CCLR1, TCNT is cleared by compare-match A CCLR0 2 to 0 CKS2 to CKS0 001...
Page 423: Figure 14.8 Ivg Signal/Ihg Signal/Cl4 Signal Timing Chart
Section 14 Timer Connection IVG signal OCRA (4) = OCRA (3) + OCRAR OCRA (3) = OCRA (2) + OCRAF OCRA (2) = OCRA (1) + OCRAR OCRA (1) = OCRA (0) + OCRAF OCRA 6 system clocks 6 system clocks 6 system clocks signal signal...
Page 424: Hsynco Output
Section 14 Timer Connection 14.4.7 HSYNCO Output With the HSYNCO output, the meaning of the signal source to be selected and use or non-use of modification varies according to the IHI signal source and the waveform required by external circuitry. The HSYNCO output modes are shown in table 14.10. Table 14.10 HSYNCO Output Modes Mode IHI Signal...
Page 425: Vsynco Output
Section 14 Timer Connection 14.4.8 VSYNCO Output With the VSYNCO output, the meaning of the signal source to be selected and use or non-use of modification varies according to the IVI signal source and the waveform required by external circuitry. The VSYNCO output modes are shown in table 14.11. Table 14.11 VSYNCO Output Modes Mode IVI Signal...
Page 426: Cblank Output
Section 14 Timer Connection Mode IVI Signal IVO Signal Meaning of IVO Signal Separate VSYNCI IVI signal (without fall VSYNCI input (vertical synchronization signal) mode input modification or IHI is output directly synchronization) IVI signal (without fall Meaningless unless VSYNCI input (vertical modification, with IHI synchronization signal) is synchronized with synchronization)
Page 427: Section 15 Watchdog Timer (Wdt)
Section 15 Watchdog Timer (WDT) Section 15 Watchdog Timer (WDT) This LSI incorporates two watchdog timer channels (WDT_0 and WDT_1). The watchdog timer can output an overflow signal (RESO) externally if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. Simultaneously, it can generate an internal reset signal or an internal NMI interrupt signal.
Page 428: Figure 15.1 Block Diagram Of Wdt
Section 15 Watchdog Timer (WDT) φ/2 φ/64 WOVI0 φ/128 Interrupt (Interrupt request signal) φ/512 control Clock Overflow Clock φ/2048 selection Internal NMI φ/8192 Reset (Interrupt request signal* φ/32768 control φ/131072 RESO signal* Internal clock Internal reset signal* TCNT_0 TCSR_0 interface Module bus WDT_0 φ/2...
Page 429: Input/Output Pins
Section 15 Watchdog Timer (WDT) 15.2 Input/Output Pins The WDT has the pins listed in table 15.1. Table 15.1 Pin Configuration Name Symbol Function RESO Reset output pin Output Outputs the counter overflow signal in watchdog timer mode External sub-clock EXCL Input Inputs the clock pulses to the WDT_1...
Page 430: Timer Control/Status Register (Tcsr)
Section 15 Watchdog Timer (WDT) 15.3.2 Timer Control/Status Register (TCSR) TCSR selects the clock source to be input to TCNT, and the timer mode. • TCSR_0 Bit Name Initial Value R/W Description R/(W) * Overflow Flag Indicates that TCNT has overflowed (changes from H'FF to H'00).
Page 431 Section 15 Watchdog Timer (WDT) Bit Name Initial Value R/W Description CKS2 Clock Select 2 to 0 CKS1 Selects the clock source to be input to. The overflow frequency for φ = 25 MHz is enclosed in parentheses. CKS0 000: φ/2 (frequency: 20.4 µs) 001: φ/64 (frequency: 655.3 µs) 010: φ/128 (frequency: 1.3 ms) 011: φ/512 (frequency: 5.2 ms)
Page 432 Section 15 Watchdog Timer (WDT) • TCSR_1 Bit Name Initial Value R/W Description R/(W) * Overflow Flag Indicates that TCNT has overflowed (changes from H'FF to H'00). [Setting condition] • When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset.
Page 433: Operation
Section 15 Watchdog Timer (WDT) Bit Name Initial Value R/W Description CKS2 Clock Select 2 to 0 CKS1 Selects the clock source to be input to TCNT. The overflow cycle for φ = 25 MHz and φSUB = 32.768 kHz is CKS0 enclosed in parentheses.
Page 434: Figure 15.2 Watchdog Timer Mode (Rst/Nmi = 1) Operation
Section 15 Watchdog Timer (WDT) If the RST/NMI bit of TCSR is set to 1, when the TCNT overflows, an internal reset signal for this LSI is issued for 518 system clocks, and the low level signal is simultaneously output from the RESO pin for 132 states, as shown in figure 15.2.
Page 435: Interval Timer Mode
Section 15 Watchdog Timer (WDT) 15.4.2 Interval Timer Mode When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows, as shown in figure 15.3. Therefore, an interrupt can be generated at intervals.
Page 436: Reso Signal Output Timing
Section 15 Watchdog Timer (WDT) RESO RESO Signal Output Timing RESO RESO 15.4.3 When TCNT overflows in watchdog timer mode, the OVF bit in TCSR is set to 1. When the RST/NMI bit is 1 here, the internal reset signal is generated for the entire LSI. At the same time, the low level signal is output from the RESO pin.
Page 437: Usage Notes
Section 15 Watchdog Timer (WDT) 15.6 Usage Notes 15.6.1 Notes on Register Access The watchdog timer’s registers, TCNT and TCSR differ from other registers in being more difficult to write to. The procedures for writing to and reading from these registers are given below.
Page 438: Conflict Between Timer Counter (Tcnt) Write And Increment
Section 15 Watchdog Timer (WDT) 15.6.2 Conflict between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 15.7 shows this operation. TCNT write cycle φ...
Page 439: System Reset By Reso Signal
Section 15 Watchdog Timer (WDT) System Reset by RESO RESO Signal RESO RESO 15.6.5 Inputting the RESO output signal to the RESO pin of this LSI prevents the LSI from being initialized correctly; the RESO signal must not be logically connected to the RES pin of the LSI. To reset the entire system by the RESO signal, use the circuit as shown in figure 15.8.
Page 440 Section 15 Watchdog Timer (WDT) Rev. 3.00 Jan 25, 2006 page 386 of 872 REJ09B0286-0300...
Page 441: Section 16 Serial Communication Interface (Sci, Irda, And Crc)
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Section 16 Serial Communication Interface (SCI, IrDA, and CRC) This LSI has three independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Asynchronous serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA).
Page 442 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Asynchronous Mode: • Data length: 7 or 8 bits • Stop bit length: 1 or 2 bits • Parity: Even, odd, or none • Receive error detection: Parity, overrun, and framing errors •...
Page 443: Figure 16.1 Block Diagram Of Sci_1
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Module data bus SCMR φ Baud rate φ/4 RxD1 generator φ/16 Transmission/ φ/64 reception control TxD1 Parity generation Clock Parity check External clock SCK1 Legend: RSR : Receive shift register : Serial control register RDR : Receive data register : Serial status register TSR : Transmit shift register...
Page 444: Figure 16.2 Block Diagram Of Sci_0 And Sci_2
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Module data bus SCMR φ Baud rate RxD0/ φ/4 generator RxD2 SEMR φ/16 TxD0/ SCIDTER φ/64 TxD2 Transmission/ reception control Parity generation Parity check Clock SSE0I/ SSE2I RFU activation request CKE1 Average transfer rate generator At 10.667-MHz...
Page 445: Input/Output Pins
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.2 Input/Output Pins Table 16.1 shows the input/output pins for each SCI channel. Table 16.1 Pin Configuration Symbol * Channel Input/Output Function SCK0 Input/Output Channel 0 clock input/output RxD0 Input Channel 0 receive data input TxD0 Output Channel 0 transmit data output...
Page 446: Receive Shift Register (Rsr)
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) • Serial interface control register (SCICR) * • Serial enhanced mode register (SEMR) * • Serial RFU enable register (SCIDTER) * Notes: 1. SCICR is not available in SCI_0 or SCI_2. 2.
Page 447: Serial Mode Register (Smr)
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.3.5 Serial Mode Register (SMR) SMR is used to set the SCI’s serial transfer format and select the baud rate generator clock source. Some bits in SMR have different functions in normal mode and smart card interface mode. Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0) Bit Name Initial Value...
Page 448 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Bit Name Initial Value Description Multiprocessor Mode (enabled only in asynchronous mode) When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode. CKS1 Clock Select 1,0 CKS0...
Page 449 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Bit Name Initial Value Description Parity Mode (valid only when the PE bit is 1 in asynchronous mode) 0: Selects even parity 1: Selects odd parity For details on the usage of this bit in smart card interface mode, see section 16.7.2, Data Format (Except in Block Transfer Mode).
Page 450: Serial Control Register (Scr)
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.3.6 Serial Control Register (SCR) SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt requests, and selection of the transfer clock source. For details on interrupt requests, see section 16.9, Interrupt Sources.
Page 451 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Bit Name Initial Value Description CKE1 Clock Enable 1,0 CKE0 These bits select the clock source and SCK pin function. Asynchronous mode 00: Internal clock (SCK pin functions as I/O port.) 01: Internal clock (Outputs a clock of the same frequency as the bit rate from the SCK pin.)
Page 452: Serial Status Register (Ssr)
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1) Bit Name Initial Value Description Transmit Interrupt Enable When this bit is set to 1,a TXI interrupt request is enabled.
Page 453 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0) Bit Name Initial Value Description R/(W) * TDRE Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] •...
Page 454 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Bit Name Initial Value Description R/(W) * ORER Overrun Error [Setting condition] • When the next serial reception is completed while RDRF = 1 [Clearing condition] • When 0 is written to ORER after reading ORER = 1 R/(W) * Framing Error...
Page 455 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Bit Name Initial Value Description Multiprocessor Bit MPB stores the multiprocessor bit in the receive frame. When the RE bit in SCR is cleared to 0 its previous state is retained. MPBT Multiprocessor Bit Transfer MPBT stores the multiprocessor bit to be added to...
Page 456 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Bit Name Initial Value Description R/(W) * Receive Data Register Full RDRF Indicates that receive data is stored in RDR. [Setting condition] • When serial reception ends normally and receive data is transferred from RSR to RDR [Clearing conditions] •...
Page 457 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Bit Name Initial Value Description TEND Transmit End TEND is set to 1 when the receiving end acknowledges no error signal and the next transmit data is ready to be transferred to TDR. [Setting conditions] •...
Page 458: Smart Card Mode Register (Scmr)
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.3.8 Smart Card Mode Register (SCMR) SCMR selects smart card interface mode and its format. Bit Name Initial Value Description 7 to — All 1 Reserved These bits are always read as 1 and cannot be modified.
Page 459: Bit Rate Register (Brr)
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 16.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and clocked synchronous mode, and smart card interface mode.
Page 460: Table 16.3 Brr Settings For Various Bit Rates (Asynchronous Mode)
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Table 16.3 BRR Settings for Various Bit Rates (Asynchronous Mode) Operating Frequency φ φ φ φ (MHz) 2.097152 2.4576 Bit Rate Error Error Error Error (bit/s) 0.03 –0.04 –0.26 0.03 0.16 0.21 0.00 0.16...
Page 461 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Operating Frequency φ φ φ φ (MHz) 6.144 7.3728 Bit Rate Error Error Error Error (bit/s) –0.44 0.08 –0.07 0.03 0.16 0.00 0.00 0.16 0.16 0.00 0.00 0.16 0.16 0.00 0.00 0.16 1200 0.16...
Page 462 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Operating Frequency φ φ φ φ (MHz) 14.7456 17.2032 Bit Rate Error Error Error Error (bit/s) –0.17 0.70 0.03 0.48 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 1200 0.16...
Page 463: Table 16.4 Maximum Bit Rate For Each Frequency (Asynchronous Mode)
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Table 16.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) Maximum Maximum Bit Rate Bit Rate φ φ φ φ (MHz) φ φ φ φ (MHz) (bit/s) (bit/s) 62500 9.8304 307200 2.097152 65536 312500...
Page 464: Table 16.6 Brr Settings For Various Bit Rates (Clocked Synchronous Mode)
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Table 16.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency φ φ φ φ (MHz) Rate (bit/s) — — — — — — — — — — — —...
Page 465: Table 16.8 Brr Settings For Various Bit Rates (Smart Card Interface Mode, N = 0, S = 372)
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Table 16.8 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, s = 372) Operating Frequency φ φ φ φ (MHz) 7.1424 10.0000 10.7136 13.0000 Bit Rate Error Error Error...
Page 466: Serial Interface Control Register (Scicr)
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.3.10 Serial Interface Control Register (SCICR) SCICR controls IrDA operation of SCI_1. Bit Name Initial Value Description IrDA Enable Specifies SCI_1 I/O pins for either normal SCI or IrDA. 0: TxD1/IrTxD and RxD1/IrRxD pins function as TxD1 and RxD1 pins, respectively 1: TxD1/IrTxD and RxD1/IrRxD pins function as IrTxD and IrRxD pins, respectively...
Page 467 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Bit Name Initial Value Description SCI Select Enable Enables/disables the external pins to select the SCI functions when the external clock is supplied in clocked synchronous mode. 0: Disables the external pins to select the SCI functions (normal) 1: Enables the external pins to select the SCI functions...
Page 468 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Bit Name Initial Value Description ACS4 Asynchronous Mode Clock Source Select ACS2 These bits specify the clock source and the average ACS1 transfer rate in asynchronous mode. ACS0 These bits are valid only when external clock is supplied in asynchronous mode.
Page 469 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Bit Name Initial Value Description ACS4 1000: Average transfer rate operation at 115.196 ACS2 kbps when the system clock frequency is 16 ACS1 MHz (operated using the basic clock with a ACS0 frequency 16 times the transfer clock frequency)
Page 470: Serial Rfu Enable Register_0 And 2 (Scidter_0 And Scidter_2)
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.3.12 Serial RFU Enable Register_0 and 2 (SCIDTER_0 and SCIDTER_2) SCIDTER_0 and SCIDTER_2 enable or disable the RFU activation requests by SCI_0 and SCI_2, respectively. Initial Bit Name Value Description TDRE_DTE TERE Data Transfer Enable Enables/disables the RFU to be activated by TDRE = 1.
Page 471: Operation In Asynchronous Mode
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.4 Operation in Asynchronous Mode Figure 16.3 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transmit/receive data, a parity bit, and finally stop bits (high level).
Page 472: Data Transfer Format
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.4.1 Data Transfer Format Table 16.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, see section 16.5, Multiprocessor Communication Function.
Page 473: Receive Data Sampling Timing And Reception Margin In Asynchronous Mode
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization.
Page 474: Clock
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s transfer clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR.
Page 475: Serial Enhanced Mode Clock
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.4.4 Serial Enhanced Mode Clock SCI_0 and SCI_2 can be operated not only based on the clocks described in section 16.4.3, Clock, but based on the following clocks, which are specified by the serial enhanced mode registers, SEMR_0 and SEMR_2.
Page 476: Figure 16.6 Basic Clock Examples When Average Transfer Rate Is Selected (1)
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Figure 16.6 Basic Clock Examples When Average Transfer Rate Is Selected (1) Rev. 3.00 Jan 25, 2006 page 422 of 872 REJ09B0286-0300...
Page 477: Figure 16.7 Basic Clock Examples When Average Transfer Rate Is Selected (2)
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Figure 16.7 Basic Clock Examples When Average Transfer Rate Is Selected (2) Rev. 3.00 Jan 25, 2006 page 423 of 872 REJ09B0286-0300...
Page 478: Sci Initialization (Asynchronous Mode)
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.4.5 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as shown in figure 16.8. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure.
Page 479: Serial Data Transmission (Asynchronous Mode)
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.4.6 Serial Data Transmission (Asynchronous Mode) Figure 16.9 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR.
Page 480: Figure 16.10 Sample Serial Transmission Flowchart
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) [1] SCI initialization: Initialization The TxD pin is automatically designated as the transmit data Start transmission output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is Read TDRE flag in SSR enabled.
Page 481: Serial Data Reception (Asynchronous Mode)
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.4.7 Serial Data Reception (Asynchronous Mode) Figure 16.11 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit.
Page 482: Table 16.11 Ssr Status Flags And Receive Data Handling
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Table 16.11 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data.
Page 483: Figure 16.12 Sample Serial Reception Flowchart (1)
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) [1] SCI initialization: Initialization The RxD pin is automatically designated as the receive data input Start reception pin. [2] [3] Receive error processing and break detection: Read ORER, PER, and If a receive error occurs, read the FER flags in SSR ORER, PER, and FER flags in SSR to identify the error.
Page 484: Figure 16.12 Sample Serial Reception Flowchart (2)
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Error processing ORER = 1 Overrun error processing FER = 1 Break? Framing error processing Clear RE bit in SCR to 0 PER = 1 Parity error processing Clear ORER, PER, and FER flags in SSR to 0 <End>...
Page 485: Multiprocessor Communication Function
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data.
Page 486: Multiprocessor Serial Data Transmission
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Transmitting station Serial communication line Receiving Receiving Receiving Receiving station A station B station C station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial H'01 H'AA data (MPB = 1)
Page 487: Multiprocessor Serial Data Reception
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) [1] SCI initialization: Initialization The TxD pin is automatically designated as the transmit data Start transmission output pin. After the TE bit is set to 1, a frame of 1s is output, and Read TDRE flag in SSR transmission is enabled.
Page 488: Figure 16.15 Example Of Sci Operation In Reception (Example With 8-Bit Data, Multiprocessor Bit, One Stop Bit)
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 16.15 shows an example of SCI operation for multiprocessor format reception.
Page 489: Figure 16.16 Sample Multiprocessor Serial Reception Flowchart (1)
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) [1] SCI initialization: Initialization The RxD pin is automatically designated as the receive data input pin. Start reception [2] ID reception cycle: Set the MPIE bit in SCR to 1. Set MPIE bit in SCR to 1 [3] SCI status check, ID reception and Read ORER and FER flags in SSR comparison:...
Page 490: Figure 16.16 Sample Multiprocessor Serial Reception Flowchart (2)
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Error processing ORER = 1 Overrun error processing FER = 1 Break? Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 <End>...
Page 491: Operation In Clocked Synchronous Mode
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.6 Operation in Clocked Synchronous Mode Figure 16.17 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in transfer data consists of 8-bit data.
Page 492: Serial Data Transmission (Clocked Synchronous Mode)
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) set to 1. However, clearing the RE bit to 0 does not initialize the RDRF, PER, FER, and ORER flags in SSR, or RDR. [1] Set the clock selection in SCR. Be sure Start initialization to clear bits RIE, TIE, TEIE, and MPIE, TE and RE to 0.
Page 493: Figure 16.19 Sample Sci Transmission Operation In Clocked Synchronous Mode
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated. Because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled.
Page 494: Figure 16.20 Sample Serial Transmission Flowchart
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) [1] SCI initialization: Initialization The TxD pin is automatically designated as the transmit data output Start transmission pin. [2] SCI status check and transmit data Read TDRE flag in SSR write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
Page 495: Serial Data Reception (Clocked Synchronous Mode)
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 16.21 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the receive data in RSR.
Page 496: Figure 16.22 Sample Serial Reception Flowchart
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) [1] SCI initialization: Initialization The RxD pin is automatically designated as the receive data input pin. Start reception [2] [3] Receive error processing: If a receive error occurs, read the Read ORER flag in SSR ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0.
Page 497: Simultaneous Serial Data Transmission And Reception (Clocked Synchronous Mode)
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 16.23 shows a sample flowchart for simultaneous serial transmit and receive operations. After initializing the SCI, the following procedure should be used for simultaneous serial data transmit and receive operations.
Page 498: Figure 16.23 Sample Flowchart Of Simultaneous Serial Transmission And Reception
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) [1] SCI initialization: Initialization The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data Start transmission/reception input pin, enabling simultaneous transmit and receive operations.
Page 499: Smart Card Interface Description
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.7 Smart Card Interface Description The SCI supports the IC card (smart card) interface based on the ISO/IEC 7816-3 (Identification Card) standard as an enhanced serial communication interface function. Smart card interface mode can be selected using the appropriate register.
Page 500: Data Format (Except In Block Transfer Mode)
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.7.2 Data Format (Except in Block Transfer Mode) Figure 16.25 shows the data transfer formats in smart card interface mode. • One frame contains 8-bit data and a parity bit in asynchronous mode. •...
Page 501: Block Transfer Mode
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) For the direct convention type, logic levels 1 and 0 correspond to states Z and A, respectively, and data is transferred with LSB-first as the start character, as shown in figure 16.26. Therefore, data in the start character in the figure is H'3B.
Page 502: Figure 16.28 Receive Data Sampling Timing In Smart Card Interface Mode (When Clock Frequency Is 372 Times The Bit Rate)
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) rising edges of the basic clock pulses so that it can be latched at the center of each bit as shown in figure 16.28. The reception margin here is determined by the following formula. D –...
Page 503: Initialization
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.7.5 Initialization Before starting transmitting and receiving data, initialize the SCI using the following procedure. Initialization is also necessary before switching from transmission to reception and vice versa. 1. Clear the TE and RE bits in SCR to 0. 2.
Page 504: Serial Data Transmission (Except In Block Transfer Mode)
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.7.6 Serial Data Transmission (Except in Block Transfer Mode) Data transmission in smart card interface mode (except in block transfer mode) is different from that in normal serial communication interface mode in that an error signal is sampled and data is re-transmitted.
Page 505: Figure 16.29 Data Re-Transfer Operation In Sci Transmission Mode
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) (n + 1) th nth transfer frame Re-transfer frame transfer frame (DE) D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4 TDRE Transfer frorm TDR to TSR...
Page 506: Figure 16.31 Sample Transmission Flowchart
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Start Initialization Start transmission ERS = 0 ? Error processing TEND = 1 ? Write data to TDR and clear TDRE flag in SSR to 0 All data transmitted? ERS = 0 ? Error processing TEND = 1 ? Clear TE bit in SCR to 0...
Page 507: Serial Data Reception (Except In Block Transfer Mode)
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.7.7 Serial Data Reception (Except in Block Transfer Mode) Data reception in smart card interface mode is identical to that in normal serial communication interface mode. Figure 16.32 shows the data re-transfer operation during reception. 1.
Page 508: Clock Output Control
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Start Initialization Start reception ORER = 0 and PER = 0? Error processing RDRF = 1 ? Read data from RDR and clear RDRF flag in SSR to 0 All data received? Clear RE bit in SCR to 0 Figure 16.33 Sample Reception Flowchart 16.7.8...
Page 509: Figure 16.34 Clock Output Fixing Timing
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) CKE0 Specified pulse width Specified pulse width Figure 16.34 Clock Output Fixing Timing At power-on and transitions to/from software standby mode, use the following procedure to secure the appropriate clock duty ratio. At Power-On: To secure the appropriate clock duty ratio simultaneously with power-on, use the following procedure.
Page 510: Irda Operation
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Software Normal operation Normal operation standby [1] [2] [3] [4] [5] Figure 16.35 Clock Stop and Restart Procedure 16.8 IrDA Operation IrDA operation can be used with SCI_1. Figure 16.36 shows an IrDA block diagram. If the IrDA function is enabled using the IrE bit in SCICR, the TxD1 and RxD1 pins in SCI_1 are allowed to encode and decode the waveform based on the IrDA standard version 1.0 (function as the IrTxD and IrRxD pins).
Page 511: Figure 16.37 Irda Transmission And Reception
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) The high-level pulse width is defined to be 1.41 µs at minimum and (3/16 + 2.5%) × bit rate or (3/16 × bit rate) +1.08 µs at maximum. For example, when the frequency of system clock φ is 20 MHz, a high-level pulse width of at least 1.4 µs to 1.6 µs can be specified.
Page 512: Table 16.12 Ircks2 To Ircks0 Bit Settings
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Table 16.12 IrCKS2 to IrCKS0 Bit Settings Bit Rate (bps) (Upper Row)/Bit Interval × × × × 3/16 (µs) (Lower Row) Operating 2400 9600 19200 38400 57600 115200 Frequency φ φ φ φ (MHz) 78.13 19.53 9.77...
Page 513: Interrupt Sources
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.9 Interrupt Sources 16.9.1 Interrupts in Normal Serial Communication Interface Mode Table 16.13 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR.
Page 514: Interrupts In Smart Card Interface Mode
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Table 16.13 SCI Interrupt Sources Channel Name Interrupt Source Interrupt Flag DTC Activation Priority ERI0 Receive error ORER, FER, PER Not possible High RXI0 Receive data full RDRF Possible TXI0 Transmit data empty TDRE Possible TEI0...
Page 515: Usage Notes
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Data transmission/reception using the DTC is also possible in smart card interface mode, similar to in the normal SCI mode. In transmission, the TEND and TDRE flags in SSR are simultaneously set to 1, thus generating a TXI interrupt request.
Page 516: 16.10.3 Mark State And Break Detection
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.10.3 Mark State and Break Detection When the TE bit in SCR is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are determined by DR and DDR of the port. This can be used to set the TxD pin to mark state (high level) or send a break during serial data transmission.
Page 517: 16.10.7 Sci Operations During Mode Transitions
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) TDRE Serial data Note: When external clock is supplied, t must be more than four clock cycles. Figure 16.38 Sample Transmission using DTC in Clocked Synchronous Mode 16.10.7 SCI Operations during Mode Transitions Transmission: Before making the transition to module stop, software standby, or sub-sleep mode, stop all transmit operations (TE = TIE = TEIE = 0).
Page 518: Figure 16.39 Sample Flowchart For Mode Transition During Transmission
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Transmission [1] Data being transmitted is lost All data transmitted? halfway. Data can be normally transmitted from the CPU by setting TE to 1, reading SSR, writing to TDR, and clearing Read TEND flag in SSR TDRE to 0 after mode cancellation;...
Page 519: Figure 16.41 Pin States During Transmission In Clocked Synchronous Mode (Internal Clock)
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Transition to Software standby Transmission start Transmission end software standby mode cancelled mode TE bit Port output pin input/output Port High output * Marking output Last TxD bit retained Port input/output input/output output pin SCI TxD output...
Page 520: 16.10.8 Notes On Switching From Sck Pins To Port Pins
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.10.8 Notes on Switching from SCK Pins to Port Pins When SCK pins are switched to port pins after transmission has completed, pins are enabled for port output after outputting a low pulse of half a cycle as shown in figure 16.43. Low pulse of half a cycle SCK/Port 1.
Page 521: Crc Operation Circuit
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.11 CRC Operation Circuit The cyclic redundancy check (CRC) operation circuit detects errors in data blocks. 16.11.1 Features The features of the CRC operation circuit are listed below. • CRC code generated for any desired data length in an 8-bit unit •...
Page 522 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) CRC Control Register (CRCCR): CRCCR initializes the CRC operation circuit, switches the operation mode, and selects the generating polynomial. Bit Name Initial Value Description DORCLR CRCDOR Clear Setting this bit to 1 clears CRCDOR to H'0000. 6 to 3 —...
Page 523: 16.11.3 Crc Operation Circuit Operation
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.11.3 CRC Operation Circuit Operation The CRC operation circuit generates a CRC code for LSB-first/MSB-first communications. An example in which a CRC code for hexadecimal data H'F0 is generated using the X 1 polynomial with the G1 and G0 bits in CRCCR set to B'11 is shown below.
Page 524: Figure 16.48 Lsb-First Data Reception
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 1. Serial reception (LSB first) Data CRC code Input 2. Write H'83 to CRCCR 3. Write H'F0 to CRCDIR CRCCR CRCDIR CRCDOR clearing CRC code generation CRCDORH CRCDORH CRCDORL CRCDORL 4. Write H'8F to CRCDIR 5.
Page 525: Figure 16.49 Msb-First Data Reception
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 1. Serial reception (MSB first) Data CRC code Input 2. Write H'83 to CRCCR 3. Write H'F0 to CRCDIR CRCCR CRCDIR CRCDOR clearing CRC code generation CRCDORH CRCDORH CRCDORL CRCDORL 4. Write H'EF to CRCDIR 5.
Page 526: 16.11.4 Note On Crc Operation Circuit
Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.11.4 Note on CRC Operation Circuit Note that the sequence to transmit the CRC code differs between LSB-first transmission and MSB-first transmission. 1. CRC code generation After specifying the operation method, write data to CRCDIR in the sequence of (1) → (2) → (3) → (4). (1) →...
Page 527: Section 17 I C Bus Interface (Iic)
Section 17 I C Bus Interface (IIC) Section 17 I C Bus Interface (IIC) This LSI has an I C bus interface (IIC) of two channels. The I C bus interface conforms to and provides a subset of the Philips I C bus (inter-IC bus) interface functions.
Page 528 Section 17 I C Bus Interface (IIC) • Direct bus drive Two pins, SCL and SDA, function as NMOS open-drain outputs when the bus drive function is selected. • Operation using the operation reservation adapter Figure 17.1 shows a block diagram of the I C bus interface.
Page 529: Figure 17.1 Block Diagram Of I
Section 17 I C Bus Interface (IIC) Adapter Timeout decision ICCNT circuit ICCRX Command control ICCMD ICSRA ICSRB ICSRC φ ICCR Clock control Noise ICMR canceler Bus state decision ICSR circuit Arbitration ICDRX(W) decision circuit ICDRT Output data conrol ICDRS circuit ICDRX(R) ICDRR...
Page 530: Input/Output Pins
Section 17 I C Bus Interface (IIC) (Master) This LSI (Slave 1) (Slave 2) Figure 17.2 I C Bus Interface Connections (Example: This LSI as Master) 17.2 Input/Output Pins Table 17.1 summarizes the input/output pins used by the I C bus interface. Table 17.1 Pin Configuration Channel Symbol...
Page 531: I 2 C Bus Data Register (Icdr)
Section 17 I C Bus Interface (IIC) • I C bus data register (ICDR) • Slave address register (SAR) • Second slave address register (SARX) • I C bus mode register (ICMR) • I C bus control register (ICCR) • I C bus status register (ICSR) •...
Page 532 Section 17 I C Bus Interface (IIC) ICDR can be written to and read from only when the ICE bit is set to 1 in ICCR. The initial value of ICDR is undefined. The ICDRE and ICDRF flags are set and cleared under the conditions shown below. Setting the ICDRE and ICDRF flags affects the status of the interrupt flags.
Page 533 Section 17 I C Bus Interface (IIC) Bit Name Initial Value R/W Description — ICDRF — — Receive Data Register Full [Setting condition] • When data is transferred from the shift register to the receive buffer (Data transfer from the shift register to the receive buffer if there is receive data in the shift register when ICDRF = 0 in receive mode) (Data is not transferred from the shift register to the...
Page 534: Slave Address Register (Sar)
Section 17 I C Bus Interface (IIC) 17.3.2 Slave Address Register (SAR) SAR sets the slave address and selects the communication format. When the LSI is in slave mode with the addressing format selected, if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device specified by the master device.
Page 535: Second Slave Address Register (Sarx)
Section 17 I C Bus Interface (IIC) 17.3.3 Second Slave Address Register (SARX) SARX sets the second slave address and selects the communication format. In slave mode, transmit/receive operations by the DTC are possible when the received address matches the second slave address.
Page 536: I 2 C Bus Mode Register (Icmr)
Section 17 I C Bus Interface (IIC) 17.3.4 C Bus Mode Register (ICMR) ICMR sets the communication format and transfer rate. It can only be accessed when the ICE bit in ICCR is set to 1. Bit Name Initial Value R/W Description MSB-First/LSB-First Select 0: MSB-first...
Page 537 Section 17 I C Bus Interface (IIC) Bit Name Initial Value R/W Description Bit Counter 2 to 0 These bits specify the number of bits to be transferred next. With the I C bus format, the data is transferred with one additional acknowledge bit.
Page 538: Table 17.3 I 2 C Transfer Rate
Section 17 I C Bus Interface (IIC) Table 17.3 I C Transfer Rate STCR ICMR Transfer Rate Bit 6/5 Bit 5 Bit 4 Bit 3 φ φ φ φ = 5 φ φ φ φ = 8 φ φ φ φ = 10 φ...
Page 539: I 2 C Bus Control Register (Iccr)
Section 17 I C Bus Interface (IIC) 17.3.5 C Bus Control Register (ICCR) ICCR consists of the control bits and interrupt request flags of the I C bus interface. Bit Name Initial Value R/W Description C Bus Interface Enable 0: This module is stopped and disconnected from the SCL and SDA pins.
Page 540 Section 17 I C Bus Interface (IIC) Bit Name Initial Value R/W Description Master/Slave Select Transmit/Receive Select 00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode Both these bits will be cleared by hardware when they lose in a bus conflict in master mode of the I C bus format.
Page 541 Section 17 I C Bus Interface (IIC) Bit Name Initial Value R/W Description ACKE Acknowledge Bit Decision Selection 0: The value of the received acknowledge bit is ignored, and continuous transfer is performed. The value of the received acknowledge bit is not indicated by the ACKB bit in ICSR, which is always 0.
Page 542 Section 17 I C Bus Interface (IIC) Bit Name Initial Value R/W Description R/(W) * I IRIC C Bus Interface Interrupt Request Flag Indicates that the IIC module has issued an interrupt request to the CPU. This flag is set at different times depending on the FS bit in SAR, the FSX bit in SARX, and the WAIT bit in ICMR.
Page 543 Section 17 I C Bus Interface (IIC) Bit Name Initial Value R/W Description Clocked synchronous serial format mode: • At the end of data transfer (rise of the 8th transmit/receive clock with serial format selected) • When a start condition is detected with serial format selected When the ICDRE or ICDRF flag is set to 1 in any operating mode:...
Page 544: Table 17.4 Flags And Transfer States
Section 17 I C Bus Interface (IIC) Table 17.4 Flags and Transfer States Operating Mode BBSY ESTP STOP IRTR AASX AL ACKB ICDRE ICDRF State  Master 0↓ 0↓ 0↓ Idle state (flag clearing required) mode  1↑ 1↑ 1↑ Start condition detected ...
Page 545 Section 17 I C Bus Interface (IIC) Operating Mode BBSY ESTP STOP IRTR AASX AL ACKB ICDRE ICDRF State       Slave 1↑ Transmission end (when ACKB mode = 1 received) 1↑/0 *    ...
Page 546: I 2 C Bus Status Register (Icsr)
Section 17 I C Bus Interface (IIC) 17.3.6 C Bus Status Register (ICSR) ICSR consists of status flags. Also see table 17.4. Initial Name Value Description R/(W) * Error Stop Condition Detection Flag ESTP This bit is valid in I C bus format slave mode.
Page 547 Section 17 I C Bus Interface (IIC) Initial Name Value Description R/(W) * Second Slave Address Recognition Flag AASX In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in SARX.
Page 548 Section 17 I C Bus Interface (IIC) Initial Name Value Description R/(W) * Slave Address Recognition Flag In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected.
Page 549 Section 17 I C Bus Interface (IIC) Initial Name Value Description ACKB Acknowledge Bit Stores acknowledge data. Transmit mode: [Setting condition] • When 1 is received as the acknowledge bit when ACKE = 1 in transmit mode [Clearing conditions] • When 0 is received as the acknowledge bit when ACKE = 1 in transmit mode •...
Page 550: Iic Operation Reservation Adapter Control Register (Iccrx)
Section 17 I C Bus Interface (IIC) 17.3.7 IIC Operation Reservation Adapter Control Register (ICCRX) ICCRX controls the operation of the IIC operation reservation adapter. Bit Name Initial Value Description ICXE IIC Operation Reservation Adapter Enable Selects whether to control the conventional IIC module or enable and control the IIC operation reservation adapter.
Page 551: Iic Operation Reservation Adapter Status Register A (Icsra)
Section 17 I C Bus Interface (IIC) Bit Name Initial Value Description AASHIT Slave Address Match 0: In master mode or slave address does not match 1: Slave address matches ACKBX Acknowledge Bit Transmission Reserve 0: Reserves transmission of acknowledge bit 0 1: Reserves transmission of acknowledge bit 1 CLR3 —...
Page 552 Section 17 I C Bus Interface (IIC) Bit Name Initial Value Description MSTX Master/Slave State X TRSX Transmit/Receive State X 00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode These bits are automatically set by an operation reservation command.
Page 553: Iic Operation Reservation Adapter Status Register B (Icsrb)
Section 17 I C Bus Interface (IIC) 17.3.9 IIC Operation Reservation Adapter Status Register B (ICSRB) ICSRB monitors operating state transitions and error status of the IIC operation reservation adapter. Bit Name Initial Value Description R/(W) * Operation Reservation Command Write Request CREQ Interrupt Flag 0: No command write request is generated...
Page 554 Section 17 I C Bus Interface (IIC) Bit Name Initial Value Description R/(W) * Stop Condition Detection STOP 0: No stop condition is detected 1: Stop condition is detected [Clearing conditions] • When ICCMD is written to • When 0 is written to STOP after reading STOP = 1 [Setting condition] •...
Page 555 Section 17 I C Bus Interface (IIC) Bit Name Initial Value Description R/(W) * Transmit Data Disagree Error DERR 0: Normal operation 1: Transmit data disagree [Clearing conditions] • When ICCMD is written to • When 0 is written to DERR after reading DERR = 1 [Setting condition] •...
Page 556: Iic Operation Reservation Adapter Status Register C (Icsrc)
Section 17 I C Bus Interface (IIC) 17.3.10 IIC Operation Reservation Adapter Status Register C (ICSRC) ICSRC monitors the transmission/reception status of the IIC operation reservation adapter. See figure 17.3 for details on the TDRE, SDRF, and RDRF bits. Bit Name Initial Value Description R/(W) *...
Page 557 Section 17 I C Bus Interface (IIC) Bit Name Initial Value Description R/(W) * STREQ Slave Mode Transmit Data Write Request Interrupt Flag: 0: No transmit data write request is generated in slave mode 1: A transmit data write request is generated and an interrupt is requested in slave mode [Clearing conditions] •...
Page 558 Section 17 I C Bus Interface (IIC) Bit Name Initial Value Description TDRE Transmit Data Register Empty 0: Transmit buffer (ICDRT) contains transmit data 1: Transmit buffer (ICDRT) contains no transmit data; write to ICDRT is possible [Setting conditions] • When start condition is detected (when ICDRX is not written to before the start condition is detected) * •...
Page 559 Section 17 I C Bus Interface (IIC) Bit Name Initial Value Description SDRF Shift Data Register Full 0: Shift register (ICDRS) contains no receive data remaining to be read or data remaining to be transmitted 1: Shift register (ICDRS) contains receive data remaining to be read or data remaining to be transmitted [Setting condition in transmit mode] •...
Page 560 Section 17 I C Bus Interface (IIC) Bit Name Initial Value Description RDRF Receive Data Register Full 0: Receive buffer (ICDRR) contains no receive data 1: Receive buffer (ICDRR) contains receive data; read from ICDRR is possible [Setting conditions] • When transmission of first frame (address + R/W = 1) in master mode ends (rise of 9th clock) •...
Page 561: Iic Operation Reservation Adapter Data Register (Icdrx)
Section 17 I C Bus Interface (IIC) Start condition detected Rise of 9th clock in first frame TDRE = 0 TDRE = 1 SDRF = 0 SDRF = 0 Stop condition detected Rise of 9th clock Write to ICDRX Fall of 1st clock TDRE = 1 TDRE = 0 SDRF = 1...
Page 562: Iic Data Shift Register (Icdrs)
Section 17 I C Bus Interface (IIC) 17.3.12 IIC Data Shift Register (ICDRS) ICDRS is an 8-bit read-only register, which is ICDR's readable shift register (ICDRS). During transfer operation, the ICDRS values change in accordance with the frame bit count. The ICDRS values can be associated with the BBC3 to BBC0 bits in ICCNT by simultaneously reading from ICDRS and ICCNT in words.
Page 563 Section 17 I C Bus Interface (IIC) Bit Name Initial Value Description CNTE Timeout Counter Enable Starts or stops the timeout counter. 0: Stops the timeout counter and clears the internal counter 1: Operates the timeout counter STOPIMX Stop Condition Interrupt Source Mask X Selects whether to enable CREQ interrupt requests by stop conditions.
Page 564: Iic Operation Reservation Adapter Command Register (Iccmd)
Section 17 I C Bus Interface (IIC) 17.3.14 IIC Operation Reservation Adapter Command Register (ICCMD) ICCMD is an 8-bit readable/writable register that specifies an IIC operation reservation adapter command. When the reserved operation is completed, ICCMD may be automatically modified to contain the next related command.
Page 565: Table 17.5 Restrictions On Accessing Iic Registers
Section 17 I C Bus Interface (IIC) Table 17.5 Restrictions on Accessing IIC Registers Register Bit Name Description ICDR 7 to 0 — Writing is disabled. Reading/writing to this register does not initiate any data transfer. Writing has no affect on the bits. 7 to 1 SVA6 to SVA0 Write the slave address.
Page 566: Operation Reservation Commands
Section 17 I C Bus Interface (IIC) 17.4.2 Operation Reservation Commands Table 17.6 lists the operation reservation commands that can be set in ICCMD. If values other than H'A0 to H'AF, and H'C0 to H'CF are set, H'A0 is automatically set as the command. The operation reservation commands reserve various operations such as start condition issuance, stop condition issuance, data transmission (including acknowledge (ACK)/non-acknowledge (NAK) judgment), and data reception (including ACK/NAK transmission and stop condition...
Page 567: Table 17.6 Operation Reservation Commands
Section 17 I C Bus Interface (IIC) Table 17.6 Operation Reservation Commands Mode Command Description Initial value 00 IIC operation reservation adapter disabled Slave Waits for address reception (ACK transmission/NACK enabled, reception using single buffer) Waits for address reception (NAK transmission/NACK disabled, reception using single buffer) Waits for address reception (ACK transmission/NACK enabled, reception using double buffer)
Page 568: Table 17.7 Operation When The Operation Reservation Command Is Completed
Section 17 I C Bus Interface (IIC) Table 17.7 Operation When the Operation Reservation Command Is Completed Trigger of Automatic Transition Starting Transition Destination Interrupt Command Operation Operation Completion Conditions Commands Flags A0 to A3 Address Address reception AAS or ADZ = 1, A4 to A7 CREQ, reception...
Page 569 Section 17 I C Bus Interface (IIC) Trigger of Automatic Transition Starting Transition Destination Interrupt Command Operation Operation Completion Conditions Commands Flags C8 to CB ICCMD write Start condition detected — — MTREQ ICDRX write Address transmission R/W = 1 —...
Page 570: Operation
Section 17 I C Bus Interface (IIC) 17.5 Operation The I C bus interface has an I C bus format and a serial format. 17.5.1 C Bus Data Format The I C bus formats are addressing formats and an acknowledge bit is inserted. The first frame following a start condition always consists of 9 bits.
Page 571: Master Transmit Operation
Section 17 I C Bus Interface (IIC) 1–7 1–7 1–7 DATA DATA Figure 17.6 I C Bus Timing Legend: Start condition. The master device drives SDA from high to low while SCL is high. SLA: Slave address R/W: Indicates the direction of data transfer: From the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0.
Page 572 Section 17 I C Bus Interface (IIC) 5. Then the IRIC and IRTR flags are set to 1. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. 6. Write the data (slave address + R/W) to ICDR. With the I C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the first frame data following the start condition indicates the 7-bit slave address and transmit/receive...
Page 573: Master Receive Operation
Section 17 I C Bus Interface (IIC) Start condition generation (master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 (master output) Slave address Data 1 (slave output) IRIC IRTR ICDR...
Page 574: Master
Section 17 I C Bus Interface (IIC) 1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Set the WAIT bit in ICMR to 1. Clear the ACKB bit in ICSR to 0 (acknowledge data setting). 2.
Page 575: Figure 17.8 Master Receive Mode Operation Timing Example (1) (Mls = Ackb = 0, Wait = 1)
Section 17 I C Bus Interface (IIC) 13. Clear the WAIT bit in ICMR to 0 to clear wait mode. Read ICDR receive data and clear the IRIC flag to 0. Clearing of the IRIC flag should be done while WAIT = 0. (If the WAIT bit is cleared to 0 after clearing the IRIC flag and then an instruction to issue a stop condition is executed, the stop condition cannot be issued because the output level of SDA is fixed as low.) 14.
Page 576: Slave Receive Operation
Section 17 I C Bus Interface (IIC) (master output) Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 (slave output) Data 2 Data 3 Data 4 (master output) IRIC IRTR ICDR...
Page 577: Figure 17.10 Slave Receive Mode Operation Timing Example (1) (Mls = Ackb = 0)
Section 17 I C Bus Interface (IIC) Receive operations can be performed continuously by repeating steps [4] and [5]. When SDA is changed from low to high when SCL is high and the stop condition is detected, the BBSY flag in ICCR is cleared to 0.
Page 578: Figure 17.11 Slave Receive Mode Operation Timing Example (2) (Mls = Ackb = 0)
Section 17 I C Bus Interface (IIC) (master output) (slave output) Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (master output) Data 1 Data 2 (slave output) RDRF Interrupt Interrupt IRIC...
Page 579: Slave Transmit Operation
Section 17 I C Bus Interface (IIC) 17.5.5 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. The transmission procedure and operations in slave transmit mode are described below.
Page 580: Figure 17.12 Slave Transmit Mode Operation Timing Example (Mls = 0)
Section 17 I C Bus Interface (IIC) Slave receive mode Slave transmit mode (master output) (slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 (slave output) Data 1 Data 2 (master output) TDRE...
Page 581: Iric Setting Timing And Scl Control
Section 17 I C Bus Interface (IIC) 17.5.6 IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the ICDRE or ICDRF internal flag is set to 1, SCL is automatically held low after one frame has been transferred;...
Page 582: Figure 17.14 Iric Flag Timing And Scl Control (2)
Section 17 I C Bus Interface (IIC) When WAIT = 1 while FS = 0 or FSX = 0 (I C bus format, wait inserted) IRIC User processing Clear Clear IRIC IRIC (a) Data transfer ends with ICDRE = 0 for transmission or ICDRF = 0 for reception IRIC User processing Clear...
Page 583: Figure 17.15 Iric Flag Timing And Scl Control (3)
Section 17 I C Bus Interface (IIC) When FS = 1 while FSX = 1 (synchronous serial format) IRIC Clear IRIC User processing (a) Data transfer ends with ICDRE = 0 for transmission or ICDRF = 0 for reception IRIC User processing Clear IRIC Write to ICDR (transmit)
Page 584: Figure 17.16 Example Of Interrupt Flag Timing Of Operation Reservation Adapter
Section 17 I C Bus Interface (IIC) First frame Second and subsequent frames IRIC Read from or write to ICCMD Read from or write to ICCMD (a) Interrupt flag timing for request to write operation reservation commands MRREQ* SRREQ* Read from ICDRX Read from ICDRX (b) Interrupt flag timing for request to read receive data in master or slave mode MTREQ*...
Page 585: Operation Using Dtc
Section 17 I C Bus Interface (IIC) 17.5.7 Operation Using DTC This LSI provides the DTC to allow continuous data transfer. The DTC is activated when the IRTR flag is set to 1, which is one of the two interrupt flags (IRTR and IRIC). When the ACKE bit is 0, the ICDRE, IRIC, and IRTR flags are set at the end of data transmission regardless of the acknowledge bit value.
Page 586: Table 17.8 Examples Of Operation Using Dtc
Section 17 I C Bus Interface (IIC) Table 17.8 Examples of Operation Using DTC Master Transmit Master Receive Slave Transmit Slave Receive Item Mode Mode Mode Mode Slave address + Transmission by Transmission by Reception by Reception by CPU R/W bit DTC (ICDR write) CPU (ICDR write) CPU (ICDR read)
Page 587: Noise Canceler
Section 17 I C Bus Interface (IIC) Table 17.9 Examples of Operation Reservation Adapter Operation Using DTC Master Transmit Master Receive Slave Transmit Slave Receive Item Mode Mode Mode Mode Slave address + Transmission by Transmission by Not necessary Not necessary R/W bit CPU (ICDRX + CPU (ICDRX +...
Page 588: Initialization Of Internal State
Section 17 I C Bus Interface (IIC) Sampling clock SCL or Internal SDA input Match SCL or signal detector Latch Latch signal System clock cycle Sampling clock Figure 17.17 Block Diagram of Noise Canceler 17.5.9 Initialization of Internal State The IIC has a function for forcible initialization of its internal state if a deadlock occurs during communication.
Page 589: Sample Flowcharts
Section 17 I C Bus Interface (IIC) Notes on Initialization: • Interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be taken as necessary. • Basically, other register flags are not cleared either, and so flag clearing measures must be taken as necessary.
Page 590: Figure 17.18 Sample Flowchart For Master Transmit Mode
Section 17 I C Bus Interface (IIC) Start Initialize [1] Initialization Read BBSY in ICCR [2] Test the status of the SCL and SDA lines. BBSY = 0? Set MST = 1 and [3] Select master transmit mode. TRS = 1 in ICCR Set BBSY =1 and [4] Start condition issuance SCP = 0 in ICCR...
Page 591: Figure 17.19 Sample Flowchart For Master Receive Mode
Section 17 I C Bus Interface (IIC) Master receive operation Set TRS = 0 in ICCR [1] Select receive mode. Set WAIT = 1 in ICMR Set ACKB = 0 in ICSR Read ICDR [2] Start receiving. The first read is a dummy read.
Page 592: Figure 17.20 Sample Flowchart For Slave Receive Mode
Section 17 I C Bus Interface (IIC) Start Initialize Set MST = 0 and TRS = 0 in ICCR Set ACKB = 0 in ICSR Read IRIC in ICCR IRIC = 1? Read AAS and ADZ in ICSR AAS = 1 General call address processing and ADZ = 0? * Description omitted...
Page 593: Interrupt Sources
Section 17 I C Bus Interface (IIC) Slave transmit mode Clear IRIC in ICCR [1] Set transmit data for the second and subsequent bytes. [2] Wait for 1 byte to be transmitted. Write transmit data in ICDR [3] Test for end of transfer. Clear IRIC in ICCR [4] Set slave receive mode.
Page 594: Table 17.10 Iic Interrupt Sources
Section 17 I C Bus Interface (IIC) Table 17.10 IIC Interrupt Sources Enable Interrupt Channel Name Interrupt Source Flag Activation Priority IICC0 CRIC Operation reservation CREQ Not possible High command write request interrupt IICM0 MRIC Master mode receive data MRREQ Possible read request interrupt Master mode transmit data...
Page 595: Usage Notes
Section 17 I C Bus Interface (IIC) 17.7 Usage Notes 1. In master mode, if an instruction to generate a start condition is immediately followed by an instruction to generate a stop condition, neither condition will be output correctly. To output consecutive start and stop conditions, after issuing the instruction that generates the start condition, read the relevant ports, check that SCL and SDA are both low, then issue the instruction that generates the stop condition.
Page 596: Table 17.12 Permissible Scl Rise Time
Section 17 I C Bus Interface (IIC) 5. The I C bus interface specification for the SCL rise time t is 1000 ns or less (300 ns for high- speed mode). In master mode, the I C bus interface monitors the SCL line and synchronizes one bit at a time during communication.
Page 597 Section 17 I C Bus Interface (IIC) • Selecting devices whose input timing permits this output timing for use as slave devices connected to the I C bus. Table 17.13 I C Bus Timing (with Maximum Influence of t Time Indication (at Maximum Transfer Rate) [ns] C Bus Specifi- φ...
Page 598: Figure 17.22 Notes On Reading Master Receive Data
Section 17 I C Bus Interface (IIC) 7. Notes on ICDR read at end of master reception To halt reception after completion of a receive operation in master receive mode, set the TRS bit to 1 and write 0 to BBSY and SCP in ICCR. This changes the SDA pin from low to high when the SCL pin is high, and generates the stop condition.
Page 599: Figure 17.23 Flowchart And Timing Of Start Condition Issuance For Retransmission
Section 17 I C Bus Interface (IIC) Therefore, after start condition issuance is done and the start condition is generated, write the transmit data to ICDR. Figure 17.23 shows the timing of start condition issuance for retransmission, and the timing for subsequently writing data to ICDR, together with the corresponding flowchart.
Page 600: Figure 17.24 Stop Condition Issuance Timing
Section 17 I C Bus Interface (IIC) 9. Note on when I C bus interface stop condition instruction is issued In a situation where the rise time of the 9th clock of SCL exceeds the stipulated value because of a large bus load capacity or where a slave device in which a wait can be inserted by driving the SCL pin low is used, the stop condition instruction should be issued after reading SCL after the rise of the 9th clock pulse and determining that it is low, as shown in figure 17.24.
Page 601: Figure 17.26 Icdr Read And Iccr Access Timing In Slave Transmit Mode
Section 17 I C Bus Interface (IIC) 11. Note on ICDR read and ICCR access in slave transmit mode In I C bus interface slave transmit mode, do not read from ICDR or do not read from or write to ICCR during the time shaded in figure 17.26. However, such read and write operations cause no problem in interrupt handling processing that is generated in synchronization with the rising edge of the 9th clock pulse because the shaded time has passed before making the transition to interrupt handling.
Page 602: Figure 17.27 Trs Bit Set Timing In Slave Mode
Section 17 I C Bus Interface (IIC) To receive the address in slave mode, clear the TRS bit to 0 during the time indicated as (a) in figure 17.27. To release the SCL low level that is held by means of the wait function in slave mode, clear the TRS bit to and then dummy-read ICDR.
Page 603 Section 17 I C Bus Interface (IIC) 1. When having received 1 as the acknowledge bit value for the last transmit data at the end of a series of transmit operation, clear the ACKE bit in ICCR to 0 once to initialize the ACKB bit to 0.
Page 604: Figure 17.28 Iric Flag Clear Timing On Wait Operation
Section 17 I C Bus Interface (IIC) Transmit/receive Transmit/receive data data SCL = ‘L’ confirm BC2 to BC0 When BC2-0 ≥ 2 IRIC clear IRIC clear IRIC (operation example) IRIC flag clear available IRIC flag clear available IRIC flag clear unavailable Figure 17.28 IRIC Flag Clear Timing on WAIT Operation 16.
Page 605: Figure 17.29 Diagram Of Erroneous Operation When Arbitration Is Lost
Section 17 I C Bus Interface (IIC) • Arbitration is lost • The AL flag in ICSR is set to 1 C bus interface DATA1 (Master transmit mode) Transmit data match Transmit data does not match Transmit timing match Other device DATA2 DATA3 (Master transmit mode)
Page 606 Section 17 I C Bus Interface (IIC) Rev. 3.00 Jan 25, 2006 page 552 of 872 REJ09B0286-0300...
Page 607: Section 18 Universal Serial Bus Interface (Usb)
Section 18 Universal Serial Bus Interface (USB) Section 18 Universal Serial Bus Interface (USB) This LSI incorporates a universal serial bus (conforms to USB standard Rev. 1.1) function module. A USB is an interface for connecting personal computer peripheral devices. There are various types of peripheral devices on the market.
Page 608: Figure 18.1 Block Diagram Of Usb
Section 18 Universal Serial Bus Interface (USB) Internal FIFO controller EP0S FIFO EP0I FIFO EP0O FIFO EP1 FIFO Internal USDP data bus USDM USB function core EP2 FIFO DrVCC DrVSS EP3 FIFO Bus driver/ receiver Control registers transmit buffer Supplied to receive buffer each block φ...
Page 609: Input/Output Pins
Section 18 Universal Serial Bus Interface (USB) 18.2 Input/Output Pins Table 18.1 shows the USB pin configuration. Table 18.1 Pin Configuration Name Symbol Input/Output Function External clock input USEXCL Input USB external clock input pin Up-stream data + USDP Input/Output I/O pin for USB serial data Up-stream data + USDM...
Page 610 Section 18 Universal Serial Bus Interface (USB) The USB has the following registers. • Endpoint size register 1 (EPSZR1) • Endpoint data register 0S (EPDR0S) • Endpoint data register 0O (EPDR0O) • Endpoint data register 0I (EPDR0I) • Endpoint data register 1 (EPDR1) •...
Page 611: Usb Data Fifo
Section 18 Universal Serial Bus Interface (USB) • USB port control register (UPRTCR) • USB test register 0 (UTESTR0) • USB test register 1 (UTESTR1) 18.3.1 USB Data FIFO FIFOs combined with EPDRs intervene in data transfer between this LSI (slave CPU) and the USB function core.
Page 612: Endpoint Size Register 1 (Epszr1)
Section 18 Universal Serial Bus Interface (USB) 18.3.2 Endpoint Size Register 1 (EPSZR1) EPSZR1 specifies the sizes of the FIFO (number of bytes) used in USB function core endpoints 1 and 2. To use both endpoints 1 and 2 in this LSI, the size of FIFOs used for endpoints 1 and 2 must be specified as 16 bytes.
Page 613: Endpoint Data Registers 0S, 0O, 0I, 1, 2, And 3 (Epdr0S, Epdr0O, Epdr0I, Epdr1, Epdr2, And Epdr3)
Section 18 Universal Serial Bus Interface (USB) 18.3.3 Endpoint Data Registers 0S, 0O, 0I, 1, 2, and 3 (EPDR0S, EPDR0O, EPDR0I, EPDR1, EPDR2, and EPDR3) EPDRs intervene in the data transfer between the CPU and FIFOs in each host input transfer or host output transfer for the USB function core endpoints 1 and 2.
Page 614: Endpoint Valid Size Registers 0S, 0O, 0I, 1, 2, And 3 (Fvsr0S, Fvsr0O, Fvsr0I, Fvsr1, Fvsr 2, And Fvsr3)
Section 18 Universal Serial Bus Interface (USB) EPDR0I Bit Name Initial Value R/W Description 7 to 0 D7 to D0 All 0 Endpoint 0 is used for input or output transfer and EPDR0I is specified as a write-only register. EPDR1 Bit Name Initial Value R/W Description...
Page 615 Section 18 Universal Serial Bus Interface (USB) In host input transfer, FVSR is decremented by the number of bytes to be written if the slave CPU writes to EPDR and sets the EPTE bit in PTTER0; FVSR is incremented by the number of bytes to be read if the USB function core reads the FIFO and an ACK handshake is received from the host.
Page 616 Section 18 Universal Serial Bus Interface (USB) FVSR0SH, FVSR0OH, FVSR0IH, FVSR1H, FVSR2H, FVSR3H Bit Name Initial Value R/W Description — Initial Values — FVSR0SH: H'00 — FVSR0OH: H'00 — FVSR0IH: H'00 — FVSR1H: H'00 — FVSR2H: H'00 FVSR3H: H'00 FVSR0SL, FVSR0OL, FVSR0IL, FVSR1L, FVSR2L, FVSR3L Bit Name Initial Value R/W Description...
Page 617: Endpoint Direction Register 0 (Epdir0)
Section 18 Universal Serial Bus Interface (USB) 18.3.5 Endpoint Direction Register 0 (EPDIR0) EPDIR0 controls the direction of data transfer for endpoints other than endpoint 0 of the USB function core. In this LSI, EP1, EP3 and EP4 must be specified as host input transfers, EP5 as a host output transfer, and EP2 as either a host input transfer or host output transfer.
Page 618: Packet Transfer Enable Register 0 (Ptter0)
Section 18 Universal Serial Bus Interface (USB) 18.3.6 Packet Transfer Enable Register 0 (PTTER0) PTTER0 controls the FIFO valid size register used in the host input transfer of the USB function core. In the USB protocol, communication is performed using packets. The minimum unit of data transfer is a transaction.
Page 619: Usb Interrupt Enable Registers 0 And 1 (Usbier0, Usbier1)
Section 18 Universal Serial Bus Interface (USB) Bit Name Initial Value R/W Description 7, 6 — All 0 Reserved These bits are always read as 0 and cannot be modified. R/(W) * Endpoint 4 Packet Transmission Enable EP4TE Prepares the transmission of RAM-FIFO data for endpoint 4 0: Normal read value.
Page 620 Section 18 Universal Serial Bus Interface (USB) USBIER0 and USBIER1 are initialized to H'00 by a system reset or function software reset (see section 18.3.16, USB Control Registers 0 and 1 (USBCR0, USBCR1)). USBIER0 Bit Name Initial Value R/W Description —...
Page 621: Usb Interrupt Flag Registers 0 And 1 (Usbifr0, Usbifr1)
Section 18 Universal Serial Bus Interface (USB) USBIER1 Bit Name Initial Value R/W Description 7 to — All 0 Reserved These bits are always read as 0 and cannot be modified. SETCE SetConfiguration Command Detection Interrupt Enable 0: Disables SetConfiguration command detection interrupt 1: Enables SetConfiguration command detection interrupt...
Page 622 Section 18 Universal Serial Bus Interface (USB) USBIFR0 Bit Name Initial Value R/W Description Transfer Normal Completion Interrupt Status Indicates that data transfer for an USB core endpoint has been completed normally. If the TSE bit in USBIER0 is set to 1, an USBID interrupt is requested to the slave CPU.
Page 623 Section 18 Universal Serial Bus Interface (USB) Bit Name Initial Value R/W Description R/(W) * Bus Reset Interrupt Status BRSTF Indicates that the USB function core detects a bus reset by an up-stream. If the BRSTE bit in USBIER0 is set to 1, an USBID interrupt is requested to the slave CPU.
Page 624 Section 18 Universal Serial Bus Interface (USB) Bit Name Initial Value R/W Description R/(W) * Suspend IN Interrupt Status SPNDIF Indicates that the USB function core detects an idle state for a specific period or more, and detects a bus state transition from normal state to suspend state.
Page 625: Transfer Normal Completion Interrupt Flag Register 0 (Tsfr0)
Section 18 Universal Serial Bus Interface (USB) USBIFR1 Bit Name Initial Value R/W Description 7 to — All 0 Reserved These bits are always read as 0 and cannot be modified. R/(W) * SetConfiguration Command Detection Interrupt Status SETC Indicates that the USB function core detects a SetConfiguration command.
Page 626 Section 18 Universal Serial Bus Interface (USB) Bit Name Initial Value R/W Description — Reserved This bit is always read as 0 and cannot be modified. R/(W) * Endpoint 5 Transfer Success Flag EP5TS Indicates that the endpoint 5 host output transfer has been completed normally.
Page 627 Section 18 Universal Serial Bus Interface (USB) Bit Name Initial Value R/W Description R/(W) * Endpoint 3 Transfer Success Flag EP3TS Indicates that the endpoint 3 host input transfer has been completed normally. 0: Indicates that the endpoint 3 is in a transfer wait state. [Clearing condition] •...
Page 628 Section 18 Universal Serial Bus Interface (USB) Bit Name Initial Value R/W Description R/(W) * Endpoint 1 Transfer Success Flag EP1TS Indicates that the endpoint 1 host input transfer has been completed normally. 0: Indicates that the endpoint 1 is in a transfer wait state. [Clearing condition] •...
Page 629 Section 18 Universal Serial Bus Interface (USB) Bit Name Initial Value R/W Description R/(W) * Endpoint 0 Host Output Transfer Success Flag EP0OTS Indicates that the endpoint 0 host output transfer has been completed normally. Endpoint 0 host output transfer has two transactions: OUT transaction and SETUP transaction.
Page 630: Transfer Abnormal Completion Interrupt Flag Register 0 (Tffr0)
Section 18 Universal Serial Bus Interface (USB) 18.3.10 Transfer Abnormal Completion Interrupt Flag Register 0 (TFFR0) TFFR0 provides status flags (EPTF) indicating that the host input or host output transaction of each USB function core endpoint has been completed abnormally. The abnormal completion of a transaction will be detected if a NAK handshake has been received or a NAK handshake has been sent because no transfer data has been received (FVSR = FIFO size: FIFO empty) in host input transfer, if a NAK handshake has been sent because the FIFO is...
Page 631 Section 18 Universal Serial Bus Interface (USB) Bit Name Initial Value R/W Description — Reserved This bit is always read as 0 and cannot be modified. R/(W) * Endpoint 5 Transfer Failure Flag EP5TF Indicates that the endpoint 5 host output transfer has been completed abnormally.
Page 632 Section 18 Universal Serial Bus Interface (USB) Bit Name Initial Value R/W Description R/(W) * Endpoint 3 Transfer Failure Flag EP3TF Indicates that the endpoint 3 host input transfer has been completed abnormally. 0: Indicates that the endpoint 3 is in a transfer wait state. [Clearing condition] •...
Page 633 Section 18 Universal Serial Bus Interface (USB) Bit Name Initial Value R/W Description R/(W) * Endpoint 1 Transfer Failure Flag EP1TF Indicates that the endpoint 1 host input transfer has been completed abnormally. 0: Indicates that the endpoint 1 is in a transfer wait state. [Clearing condition] •...
Page 634 Section 18 Universal Serial Bus Interface (USB) Bit Name Initial Value R/W Description R/(W) * Endpoint 0 Host Output Transfer Failure Flag EP0OTF Indicates that the endpoint 0 host output transfer has been completed abnormally. Endpoint 0 host output transfer has two transactions: OUT transaction and SETUP transaction.
Page 635: Usb Control /Status Register 0 (Usbcsr0)
Section 18 Universal Serial Bus Interface (USB) 18.3.11 USB Control /Status Register 0 (USBCSR0) USBCSR0 controls the operation of the USB function core. USBCSR0 is initialized to H'00 by a system reset or function software reset (see section 18.3.16, USB Control Registers 0 and 1 (USBCR0, USBCR1)). Bit Name Initial Value R/W Description 7 to 4 —...
Page 636 Section 18 Universal Serial Bus Interface (USB) Bit Name Initial Value R/W Description R/(W) * Endpoint Information Valid EPIVLD Enables USB function core operation. To enable the USB function core operation, endpoint information must be specified. After a system reset or function software reset, the USB function core has no endpoint information.
Page 637 Section 18 Universal Serial Bus Interface (USB) Bit Name Initial Value R/W Description EP0OTC Endpoint 0O Transfer Control Controls the USB function core endpoint 0 control transfer. Clearing this bit to 0 disables the write to the EP0 OUT-FIFO. This generates a transfer abnormal completion interrupt.
Page 638: Endpoint Stall Register 0 (Epstlr0)
Section 18 Universal Serial Bus Interface (USB) Bit Name Initial Value R/W Description — R/(W) Reserved The initial value should not be changed. Note: * Writing of 0 is disabled. 18.3.12 Endpoint Stall Register 0 (EPSTLR0) EPSTLR0 stalls the USB function core endpoints. Endpoints whose EPSTL bits are set to 1 respond by a STALL handshake when a transaction has been initiated by receiving a token from the host.
Page 639 Section 18 Universal Serial Bus Interface (USB) Bit Name Initial Value R/W Description EP4STL Endpoint 5 Stall Sets endpoint 5 in a stall state. 0: Endpoint 5 is in an operating state. (Stall state can be cancelled by the ClearFeature command) [Clearing condition] (SCME = 1) •...
Page 640 Section 18 Universal Serial Bus Interface (USB) Bit Name Initial Value R/W Description EP1STL Endpoint 2 Stall Sets endpoint 2 in a stall state. 0: Endpoint 2 is in an operating state. (Stall state can be cancelled by the ClearFeature command) [Clearing condition] (SCME = 1) •...
Page 641: Endpoint Reset Register 0 (Eprstr0)
Section 18 Universal Serial Bus Interface (USB) 18.3.13 Endpoint Reset Register 0 (EPRSTR0) EPRSTR0 resets the FIFO pointers for each USB function core endpoint. Bit Name Initial Value R/W Description — Reserved This bit is always read as 0 and cannot be modified. R/(W) * Endpoint 5 Reset EP5RST Initializes endpoint 5 FIFO.
Page 642 Section 18 Universal Serial Bus Interface (USB) Bit Name Initial Value R/W Description R/(W) * Endpoint 1 Reset EP1RST Initializes endpoint 1 FIFO. 0: Normal read value 1: FVSR1 is initialized to H'0010 (EP1 FIFO size is 16 bytes) FVSR1 is initialized to H'0020 (EP1 FIFO size is 32 bytes) R/(W) * Endpoint 0I Reset EP0IRST...
Page 643: Device Resume Register (Devrsmr)
Section 18 Universal Serial Bus Interface (USB) 18.3.14 Device Resume Register (DEVRSMR) DEVRSMR has a flag that shows whether remote wakeup is enabled or disabled and a bit that controls remote wakeup of the USB function core suspend state. DEVRSMR is initialized to H'00 by a system reset or function software reset (see section 18.3.16, USB Control Registers 0 and 1 (USBCR0, USBCR1)).
Page 644: Interrupt Source Select Register 0 (Intselr0)
Section 18 Universal Serial Bus Interface (USB) 18.3.15 Interrupt Source Select Register 0 (INTSELR0) INTSELR0 selects USBIB interrupt and USBIC interrupt sources for the USB module. INTSELR0 is initialized to H'00 by a system reset or function software reset (see section 18.3.16, USB Control Registers 0 and 1 (USBCR0, USBCR1)).
Page 645 Section 18 Universal Serial Bus Interface (USB) Bit Name Initial Value R/W Description EPICS2 Interrupt C Endpoint Select 2 to 0 EPICS1 Combined with the TSELC bit, selects a USBIC interrupt source. EPICS0 000: Selects no endpoint 001: Selects endpoint 1 010: Selects endpoint 2 011: Selects endpoint 3 100: Selects endpoint 4...
Page 646: Usb Control Registers 0 And 1 (Usbcr0, Usbcr1)
Section 18 Universal Serial Bus Interface (USB) 18.3.16 USB Control Registers 0 and 1 (USBCR0, USBCR1) USBCR0 selects the USB module data input/output method and controls the operation states and reset states of each unit. USBCR1 controls clock supply to the bus driver/receiver and USB function core.
Page 647 Section 18 Universal Serial Bus Interface (USB) Bit Name Initial Value R/W Description FPLLRST 1 Function PLL Software Reset Resets the USB bus clock circuit (DPLL) in the USB function core. Setting this bit to 1 resets the DPLL in the USB function core and stops bus clock synchronization.
Page 648 Section 18 Universal Serial Bus Interface (USB) USBCR1 Bit Name Initial Value R/W Description 7 to — All 0 Reserved These bits are always read as 0 and cannot be modified. VBUSS VBUS Status Prevents bus driver/receiver feedthrough current from generating by controlling the VBUS line (USB cable) connection state.
Page 649: Usb Pll Control Register (Upllcr)
Section 18 Universal Serial Bus Interface (USB) Table 18.3 Port 6 Functions Control I/O of Driver/Receiver Compatible with PDIUSBP11A Port 6 by Philips Electronics P67 (DPLS) Input Differential input (+) P66 (DMNS) Input Differential input (–) P65 (XVERDATA) Input Data input P64 (TXDPLS) Output Differential input (+)
Page 650 Section 18 Universal Serial Bus Interface (USB) Bit Name Initial Value R/W Description 7, 6 — All 0 Reserved These bits are always read as 0 and cannot be modified. PFSEL2 PLL Frequency Select 2 Combined with the PFSEL1 and PFSEL0 bits, this bit selects the frequency of the clock to be provided to the USB operating clock generation circuit (PLL).
Page 651: Configuration Value Register (Confv)
Section 18 Universal Serial Bus Interface (USB) 18.3.18 Configuration Value Register (CONFV) CONFV stores the configuration, interface, and alternation values selected by the host by using the SetConfiguration and SetInterface command. CONFV is initialized to H'00 by a system reset or function software reset (see section 18.3.16, USB Control Registers 0 and 1 (USBCR0, USBCR1)).
Page 652: Endpoint 4 Packet Size Register (Ep4Pktszr)
Section 18 Universal Serial Bus Interface (USB) 18.3.19 Endpoint 4 Packet Size Register (EP4PKTSZR) EP4PKTSZR specifies the MaxPacketSize for endpoint 4. In this LSI, only 64 bytes can be specified as MaxPacketSize. Endpoint 4 receives transmit data from the RFU. The packet size of endpoint 4 is controlled by the USB module and transmit data is transferred from the RFU until the number of transmit data bytes reaches the value specified in EP4PKTSZR.
Page 653: Rfu/Fifo Read Request Flag Register (Udtrfr)
Section 18 Universal Serial Bus Interface (USB) 18.3.20 RFU/FIFO Read Request Flag Register (UDTRFR) UDTRFR provides a flag indicating that endpoint 5 is placed in data transfer completion state. Endpoint 5 has a 2-byte receive buffer in the USB module to temporarily store data received from the host into the receive buffer before transferring it to the RAM-FIFO by the RFU.
Page 654: Usb Mode Control Register (Usbmdcr)
Section 18 Universal Serial Bus Interface (USB) 18.3.21 USB Mode Control Register (USBMDCR) USBMDCR controls SETUP transaction operations and stall cancellation procedures. USBMDCR is initialized to H'00 by a system reset or function software reset (see section 18.3.16, USB Control Registers 0 and 1 (USBCR0, USBCR1)). Bit Name Initial Value R/W Description 7 to...
Page 655: Usb Port Control Register (Uprtcr), And Usb Test Registers 0 And 1 (Utestr0 And Utestr1)
Section 18 Universal Serial Bus Interface (USB) 18.3.22 USB Port Control Register (UPRTCR), and USB Test Registers 0 and 1 (UTESTR0 and UTESTR1) UPRTCR, UTESTR0, and UTESTR1 are used for testing. Note that values other than initial values must not be set to UPRTCR, UTESTR0, and UTESTR1. UPRTCR, UTESTR0, and UTESTR1 are initialized to H'00 by a system reset.
Page 656: Operation
Section 18 Universal Serial Bus Interface (USB) 18.4 Operation The USB is an interface for personal computer peripheral devices and is defined by the USB standard Rev. 1.1. The USB module in this LSI operates based on the USB standard Rev. 1.1. 18.4.1 USB Function Core Functions The USB function core has five endpoints.
Page 657: Table 18.4 Usb Function Core And Slave Cpu Functions
Section 18 Universal Serial Bus Interface (USB) CPU must read, interpret and execute a command from the FIFO. The slave CPU must process the remaining transactions of a control transfer using FIFOs. When the SETICNT bit is set to 1, the FIFO for EP0S is used and the SETUPF flag is set only when a GetDescriptor, SetDescriptor, or device class specific command is received.
Page 658: Operation On Receiving A Setup Token (Endpoint 0)
Section 18 Universal Serial Bus Interface (USB) The bus driver/receiver on the port unit and the USB function core process the electrical signal and signal bit stream on the USB bus line. The token, acknowledge type, and data byte are extracted, and the acknowledge and data byte are converted to electrical signals of the bit stream (no.
Page 659: Table 18.5 Packets Included In Each Transaction
Section 18 Universal Serial Bus Interface (USB) Table 18.5 Packets Included in Each Transaction Handshake Phase * Stage Token Phase Data Phase Setup stage SETUP token OUT data packet (8 bytes) ACK handshake packet (host to slave) packet (slave to host) Control write Data stage OUT token...
Page 660: Figure 18.2 Operation On Receiving A Setup Token (When Decode By The Slave Cpu Is Not Required And When Seticnt = 0)
Section 18 Universal Serial Bus Interface (USB) USB Host USB Function Core Core Interface Slave CPU Send a SETUP Receive a SETUP Automatically set token packet each flag * token packet Request an USBIA Initiate the USBIA interrupt (SETUP) interrupt processing Read USBIFR0 * Receive an OUT Send an OUT data...
Page 661: Figure 18.3 Operation On Receiving A Setup Token (When Decode By The Slave Cpu Is Required And When Seticnt = 0)
Section 18 Universal Serial Bus Interface (USB) USB Host USB Function Core Core Interface Slave CPU Automatically set Send a SETUP Receive a SETUP each flag * token packet token packet Request an USBIA Initiate the USBIA interrupt (SETUP) interrupt processing Write data to EP0O Send an OUT data Receive an OUT data...
Page 662: Figure 18.4 Operation On Receiving A Setup Token (When Decode By The Slave Cpu Is Not Required And When Seticnt = 1)
Section 18 Universal Serial Bus Interface (USB) USB Host USB Function Core Core Interface Slave CPU Send a SETUP Receive a SETUP Automatically set token packet token packet each flag * Receive an OUT data Send an OUT data Write data to EP0S FIFO packet (8 bytes) packet (8 bytes) Command data decode...
Page 663: Figure 18.5 Operation On Receiving A Setup Token (When Decode By The Slave Cpu Is Required And When Seticnt = 1)
Section 18 Universal Serial Bus Interface (USB) USB Host USB Function Core Core Interface Slave CPU Send a SETUP Receive a SETUP Automatically set token packet each flag * token packet Receive an OUT data Send an OUT data Write data to EP0S FIFO packet (8 bytes) packet (8 bytes) Command data decode...
Page 664: Operation On Receiving An Out Token (Endpoints 0, 2, And 5)
Section 18 Universal Serial Bus Interface (USB) 18.4.3 Operation on Receiving an OUT Token (Endpoints 0, 2, and 5) Figures 18.6 to 18.9 show the USB function core and LSI firmware operations when the USB function core receives an OUT token (OUT transaction). An OUT transaction is used for data stage and status stage of control transfer, interrupt transfer, and bulk transfer.
Page 665: Figure 18.7 Operation On Receiving An Out Token (Ep2-Out: Initial Fifo Is Full)
Section 18 Universal Serial Bus Interface (USB) USB Host USB Function Core Core Interface Slave CPU Send an OUT Receive an OUT token packet token packet Disable data write because Receive an OUT data Send an OUT data the EP2 FIFO is full packet (8 bytes) packet (8 bytes) Restore FVSR2...
Page 666: Figure 18.8 Operation On Receiving An Out Token (Ep5-Out: Initial Fifo Is Empty)
Section 18 Universal Serial Bus Interface (USB) USB Host USB Function Core Core Interface Slave CPU Send an OUT Receive an OUT token packet token packet Write data to the EP5 Send an OUT data Receive an OUT data receive buffer packet (64 bytes) packet (64 bytes) Request RFU...
Page 667: Figure 18.9 Operation On Receiving An Out Token (Ep5-Out: Initial Fifo Is Full)
Section 18 Universal Serial Bus Interface (USB) USB Host USB Function Core Core Interface Slave CPU Send an OUT Receive an OUT token packet token packet Write data to the EP5 Receive an OUT data Send an OUT data receive buffer packet (64 bytes) packet (64 bytes) Request RFU transmission...
Page 668: Operation On Receiving An In Token (Endpoints 0, 1, 2, 3 And 4)
Section 18 Universal Serial Bus Interface (USB) 18.4.4 Operation on Receiving an IN Token (Endpoints 0, 1, 2, 3 and 4) Figures 18.10 to 18.13 show the USB function core and LSI firmware operations when the USB function core receives an IN token (IN transaction). An IN transaction is used for data stage and status stage of control transfer, interrupt transfer, and bulk transfer.
Page 669: Figure 18.11 Operation On Receiving An In Token (Ep2-In: Initial Fifo Is Empty)
Section 18 Universal Serial Bus Interface (USB) USB Host USB Function Core Core Interface Slave CPU Disable data read because the EP2 FIFO is Receive an IN token packet Send an IN token packet empty Receive a NAK Send NAK to the host CPU handshake packet Initiate the USBID interrupt Request an USBID...
Page 670: Figure 18.12 Operation On Receiving An In Token (Ep4-In: Initial Fifo Is Full)
Section 18 Universal Serial Bus Interface (USB) Slave CPU USB Host USB Function Core Core Interface Send an IN token Receive an IN token packet packet Read data from the EP4 Send an IN data Receive an IN data transmission buffer packet (64 bytes) packet (64 bytes) Read the RAM-FIFO, send...
Page 671: Figure 18.13 Operation On Receiving An In Token (Ep4-In: Initial Fifo Is Empty)
Section 18 Universal Serial Bus Interface (USB) USB Function Core Core Interface USB Host Slave CPU Disable data read because Send an IN token packet Receive an IN token packet the EP4 transmit buffer is empty Receive a NAK Send NAK to the host CPU handshake packet Initiate the USBID interrupt Request an USBID...
Page 672: Suspend/Resume Operation
Section 18 Universal Serial Bus Interface (USB) 18.4.5 Suspend/Resume Operation The USB function core automatically enters a suspend state if the USB data line is placed in an idle state for a time equal to or greater than that specified by the USB standard Rev. 1.1. A suspend state is automatically cancelled (resumed) when the upstream (host) resumes data transfer.
Page 673: Table 18.6 Registers Initialized By Bit Uifrst Or Fsrst
Section 18 Universal Serial Bus Interface (USB) Reset State: A reset state is entered by bringing the RES pin of the LSI to low. In a reset state, registers that can be initialized and the internal status of the LSI are initialized and all pins of the LSI are placed in input state.
Page 674 Section 18 Universal Serial Bus Interface (USB) USB Bus Reset State: When a new device is connected to the USB bus or when en error recovery process is executed, the USDP/USDM pin is placed in a bus reset state for a specific period. In the USB module, the bus reset interrupt flag is set to 1 when a USB bus reset is detected.
Page 675: Usb Module Startup Sequence
Section 18 Universal Serial Bus Interface (USB) 18.4.7 USB Module Startup Sequence USB Module Configuration: The USB module is comprised of several components. To correctly operate these components and notify the host, the USB module must be started up by the firmware (this LSI’s program) according to the sequence described later.
Page 676: Table 18.7 Endpoint Information
Section 18 Universal Serial Bus Interface (USB) (c) EPINFO: Endpoint information The USB function core of this LSI can support isochronous transfer. However, due to the CPU interface specifications, the USB function core of this LSI handles only control transfer, interrupt transfer, and bulk transfer.
Page 677 Section 18 Universal Serial Bus Interface (USB) Initialization Sequence: The USB module is initialized in the sequence shown in figure 18.14. 1. The LSI is placed in a power off state or hardware standby mode. 2. Turn the power on, apply a high level to the STBY pin, and finally apply a high level to the RES pin to initiate the LSI operation.
Page 678: Figure 18.14 Operation Procedure For Initializing Usb Module
Section 18 Universal Serial Bus Interface (USB) External Event, Host USB Function Core Core Interface Slave CPU Start system operation Cancel reset (RES = 1) Check if the USB cable is connected Cancel the module stop state of the USB module Set the VBUSS bit of USBCR1 to 1 Set UPLLCR...
Page 679: Interrupt Sources
Section 18 Universal Serial Bus Interface (USB) 18.5 Interrupt Sources The USB module’s slave CPU interrupts are USBIA, USBIB, UABIC, and USBID interrupts. Tables 18.8 and 18.9 show interrupt sources and their priorities. Interrupt sources are interrupt flags of USBIRF0, USBIFR1, TSFR0, TFFR0, and UDTRFR. Each interrupt can be enabled or disabled according to each interrupt enable bit of USBIER0 and USBIER1.
Page 680: Usage Notes
Section 18 Universal Serial Bus Interface (USB) 18.6 Usage Notes 1. When activating the DTC by a USB interrupt source, correct operation is not guaranteed if the DISEL bit in DTC mode register B (MRB) is cleared to 0. Be sure to set the DISEL bit to before DTC activation.
Page 681: Section 19 Multimedia Card Interface (Mcif)
Section 19 Multimedia Card Interface (MCIF) Section 19 Multimedia Card Interface (MCIF) This LSI supports a multimedia card (MultiMediaCard™ * , hereafter referred to as MMC) interface (MCIF) * . The MCIF has two operating modes: MultiMediaCard mode (hereafter referred to as MMC mode) and SPI mode. The MCIF is a clocked-synchronous serial interface that transmits/receives data that is distinguished in terms of command and response.
Page 682: Figure 19.1 Block Diagram Of Mcif
Section 19 Multimedia Card Interface (MCIF) SPI mode: • Interface via the MCCLK pin (transfer clock output) , MCTxD pin (command transmission/data transmission) , MCRxD pin (response reception/data transmission) and MCCSA and MCCSB pins (chip select) for each MMC. Command transmission/ response reception MCCLK Module data bus...
Page 683: Input/Output Pins
Section 19 Multimedia Card Interface (MCIF) 19.2 Input/Output Pins Table 19.1 summarizes the pins of the MCIF. Table 19.1 Pin Configuration Name Function MCCLK, ExMCCLK Output Common clock output pins in MMC mode/SPI mode MCTxD, ExMCTxD Output Command/data output pins in SPI mode These pins are connected to the Data in pin on the MMC side MCRxD, ExMCRxD...
Page 684: Register Descriptions
Section 19 Multimedia Card Interface (MCIF) 19.3 Register Descriptions The MCIF has the following registers. • Mode register (MODER) • Command type register (CMDTYR) • Response type register (RSPTYR) • Transfer byte number count register (TBCR) • Transfer block number counter (TBNCR) •...
Page 685: Mode Register (Moder)
Section 19 Multimedia Card Interface (MCIF) 19.3.1 Mode Register (MODER) MODER specifies the MCIF operating mode. The two operating modes have different input/output pin functions, usable command types, and command sequence. In each mode, the following sequence should be repeated when the MCIF uses the MMC: Send a command, wait for the end of the command sequence and the end of the data busy state, and send the next command.
Page 686: Command Type Register (Cmdtyr)
Section 19 Multimedia Card Interface (MCIF) 19.3.2 Command Type Register (CMDTYR) CMDTYR specifies the command format in conjunction with RSPTYR. For details, refer to table 19.2. Bit Name Initial Value Description 7, 6 — All 0 Reserved These bits are always read as 0 and cannot be modified.
Page 687: Response Type Register (Rsptyr)
Section 19 Multimedia Card Interface (MCIF) 19.3.3 Response Type Register (RSPTYR) RSPTYR specifies the command format in conjunction with CMDTYR. For details, refer to table 19.2. Bit Name Initial Value Description 7, 6 — All 0 Reserved These bits are always read as 0 and cannot be modified.
Page 688: Table 19.2 Correspondence Between Commands And Settings Of Cmdtyr And Rsptyr
Section 19 Multimedia Card Interface (MCIF) Table 19.2 summarizes the correspondence between the commands listed in the MultiMediaCard System Specification Version 2.11 and the settings of CMDTYR and RSPTYR. In MMC mode and SPI mode, the response format is different. Also, in SPI mode, there are commands that require a data response.
Page 689 Section 19 Multimedia Card Interface (MCIF) CMDTYR RSPTYR Command resp * Abbreviation TY1, RTY2 to Index RTY4 * RTY5 RTY0 * CMD38 ERASE 100/001 CMD39M * FAST_IO CMD40M * GO_IRQ_STATE 10 * CMD42 LOCK_UNLOCK 100/001 CMD55 APP_CMD 100/001 10 * CMD56 GEN_CMD 100/001...
Page 690: Transfer Byte Number Count Register (Tbcr)
Section 19 Multimedia Card Interface (MCIF) 19.3.4 Transfer Byte Number Count Register (TBCR) TBCR specifies the number of bytes to be transferred (block size) for a block transfer command. The block size is the number of data block bytes not including the start bit (byte in SPI mode) and CRC.
Page 691: Command Registers 0 To 5 (Cmdr0 To Cmdr5)
Section 19 Multimedia Card Interface (MCIF) 19.3.6 Command Registers 0 to 5 (CMDR0 to CMDR5) A command is written to CMDR as shown in table 19.3, and a command is transmitted by setting the START bit in CMDSTRT to 1. Table 19.3 CMDR Configuration Register Contents...
Page 692: Response Registers 0 To 16, And D (Rspr0 To Rspr16, And Rsprd)
Section 19 Multimedia Card Interface (MCIF) 19.3.7 Response Registers 0 to 16, and D (RSPR0 to RSPR16, and RSPRD) The RSPR registers are eighteen 8-bit registers. RSPR0 to RSPR16 are command response registers. RSPRD is a data response register that is used in only SPI mode. The number of command response bytes differs according to the command.
Page 693: Table 19.4 Correspondence Between Number Of Command Response Bytes And Rspr Register
Section 19 Multimedia Card Interface (MCIF) Table 19.4 Correspondence between Number of Command Response Bytes and RSPR Register SPI Mode Response MMC Mode Response 1 Byte in 2 Bytes in 5 Bytes in 6 Bytes in 17 Bytes in RSPR SPI Mode SPI Mode SPI Mode...
Page 694: Command Start Register (Cmdstrt)
Section 19 Multimedia Card Interface (MCIF) 19.3.8 Command Start Register (CMDSTRT) CMDSTRT triggers the start of command transmission, representing the start of a command sequence. The following operations should be completed before the command sequence starts. • Analysis of prior command response, clearing the command response register write if necessary •...
Page 695: Operation Control Register (Opcr)
Section 19 Multimedia Card Interface (MCIF) 19.3.9 Operation Control Register (OPCR) OPCR controls command operation abort, and suspends or continues data transfer. Bit Name Initial Value Description CMDOFF Command Off Always read as 0. Aborts all command operations (MCIF command sequence) when 1 is written after a command is transmitted.
Page 696: Table 19.5 Card States In Which Command Sequence Is Halted
Section 19 Multimedia Card Interface (MCIF) Bit Name Initial Value Description DATAEN Data Enable Read as 1 during data transfer period after 1 is written. Otherwise, read as 0. Starts write data transmission by a command with write data. Resumes transfer clock output and write data transmission when the transfer clock is halted according to FIFO empty or termination of one block writing in multiblock write.
Page 697: Command Timeout Control Register (Ctocr)
Section 19 Multimedia Card Interface (MCIF) For write data transmission, the contents of the command response and data response should be analyzed, and then transmission should be triggered. In addition, the transfer clock (MCCLK) output should be temporarily halted according to FIFO full/empty, and it should be resumed when preparation has been completed.
Page 698: Data Timeout Register (Dtoutr)
Section 19 Multimedia Card Interface (MCIF) Bit Name Initial Value Description — All 0 Reserved These bits are always read as 0 and cannot be modified. CTSEL0 Command Timeout Select Specifies the number of transfer clocks from command transmission completion to response reception completion. 0: 128 transfer clocks 1: 256 transfer clocks 19.3.11 Data Timeout Register (DTOUTR)
Page 699: Card Status Register (Cstr)
Section 19 Multimedia Card Interface (MCIF) 19.3.12 Card Status Register (CSTR) CSTR indicates the MCIF status during command sequence execution. Bit Name Initial Value Description BUSY Command Busy Indicates command execution status. When the CMDOFF bit in OPCR is set to 1, this bit is cleared to 0 because the MCIF command sequence is aborted.
Page 700 Section 19 Multimedia Card Interface (MCIF) Bit Name Initial Value Description DTBUSY Data Busy Indicates command execution status. Indicates that the MMC is in the busy state during or after the command sequence of a command without data transfer, which includes the busy state in the response, or of a command with write data has been ended.
Page 701: Interrupt Control Registers 0, 1 (Intcr0, Intcr1)
Section 19 Multimedia Card Interface (MCIF) 19.3.13 Interrupt Control Registers 0, 1 (INTCR0, INTCR1) The INTCR registers enable or disable an interrupt. INTCR0 Bit Name Initial Value Description FEIE FIFO Empty Interrupt Enable When this bit is set to 1 while the INTRQ0E bit is 1, the data FIFO empty interrupt request is enabled.
Page 702 Section 19 Multimedia Card Interface (MCIF) INTCR1 Bit Name Initial Value Description INTRQ2E Source 2 Interrupt Enable 0: Disables MCIF2 interrupt to the CPU. 1: Enables MCIF2 interrupt to the CPU. INTRQ1E Source 1 Interrupt Enable 0: Disables MCIF1 interrupt to the CPU. 1: Enables MCIF1 interrupt to the CPU.
Page 703: Interrupt Status Registers 0, 1 (Intstr0, Intstr1)
Section 19 Multimedia Card Interface (MCIF) 19.3.14 Interrupt Status Registers 0, 1 (INTSTR0, INTSTR1) The INTSTR registers enable or disable the MCIFI0 to MCIFI2 interrupt requests of MCIF. INTSTR0 Bit Name Initial Value Description R/(W) * FIFO Empty Interrupt Flag 0: No interrupts 1: MCIFI0 interrupt requested.
Page 704 Section 19 Multimedia Card Interface (MCIF) Bit Name Initial Value Description R/(W) * Data Transfer End Interrupt Flag 0: No interrupts 1: MCIFI1 interrupt requested. [Setting condition] • When the number of bytes of data transfer specified in TBCR ends while DTIE = 1 in INTCR0.
Page 705 Section 19 Multimedia Card Interface (MCIF) Bit Name Initial Value Description R/(W) * DBSYI Data Busy End Interrupt Flag 0: No interrupts 1: MCIFI1 interrupt requested. [Setting condition] • When data busy state ends while DBSYIE = 1 in INTCR0. (When the DTBUSY bit in CSTR is cleared.) [Clearing condition] •...
Page 706 Section 19 Multimedia Card Interface (MCIF) INTSTR1 Bit Name Initial Value Description — All 0 Reserved These bits are always read as 0 and cannot be modified. R/(W) * CRCERI CRC Error Interrupt Flag 0: No interrupts 1: MCIFI2 interrupt requested. [Setting condition] •...
Page 707: Pin Mode Control Register (Iomcr)
Section 19 Multimedia Card Interface (MCIF) 19.3.15 Pin Mode Control Register (IOMCR) IOMCR controls chip select pin operation in SPI mode and input/output direction output pin operation in MMC mode. Bit Name Initial Value Description SPCNUM Number of SPI Mode MMCs Specifies whether one or two MMCs are to be operated in SPI mode.
Page 708: Transfer Clock Control Register (Clkon)
Section 19 Multimedia Card Interface (MCIF) Bit Name Initial Value Description MMCPE MCIF Pin Function Enable Enables/disables input/output of all MCIF input/output pins. 0: Disables all inputs/outputs. 1: Enables MCCLK, MCCMD/MCTxD, MCDAT/MCRxD, MCCSA/MCDATDIR, and MCCSB/MCCMDDIR pin inputs/outputs. Outputs of the MCCSB and MCDATDIR and MCCMDDIR pins are also disabled via the SPCNUM bit and DIRME bit, respectively.
Page 709: Mcif Activation
Section 19 Multimedia Card Interface (MCIF) 19.4 MCIF Activation The MMC is an external storage media that can be disconnected. The MCIF controls data transfer with the MMC, however, it cannot control insertion and ejection of the MMC successfully. Firmware should be used to control insertion and ejection of the MMC by using an external interrupt and general ports of this LSI.
Page 710: Operations In Mmc Mode
Section 19 Multimedia Card Interface (MCIF) 19.5 Operations in MMC Mode MMC mode is an operating mode in which the transfer clock is output from the MCCLK pin, command transmission/response receive occurs via the MCCMD pin, and data is transmitted/received via the MCDAT pin. In this mode the next command can be issued while data is being transmitted/received.
Page 711: Operation Of Relative Address Commands
Section 19 Multimedia Card Interface (MCIF) 19.5.2 Operation of Relative Address Commands The CMD7M, CMD9, CMD10, CMD13, CMD15M, CMD39M, and CMD55 are relative address commands that address the MMC by the RCA. The relative address commands are used to read MMC administration information and original information, and to change the specific MMC status.
Page 712: Figure 19.2 Example Of Command Sequence For Commands That Do Not Require Command Response
Section 19 Multimedia Card Interface (MCIF) MCCLK Command output (48 bits) MCCMD MCDAT (CMDSTRT) Command transmission started Command transmission ended START (INTSTR0) CMDIE (CSTR) CWRE Command transmission period BUSY Command sequence execution period Figure 19.2 Example of Command Sequence for Commands that Do Not Require Command Response Command sequence start Set command data to CMDR0 to CMDR4...
Page 713: Operation Of Commands Without Data Transfer
Section 19 Multimedia Card Interface (MCIF) 19.5.4 Operation of Commands without Data Transfer The broadcast and relative address commands include a number of commands that do not include data transfer. Such commands execute the desired data transfer using command arguments and command responses.
Page 714: Figure 19.4 Example Of Command Sequence For Commands Without Data Transfer (No Data Busy State)
Section 19 Multimedia Card Interface (MCIF) MCCLK Command output (48 bits) Command response reception (No busy state) MCCMD MCDAT (CMDSTRT) Command transmission Response reception started completed START (INTSTR0) CMDI CRPI DBSYI (CSTR) CWRE Command transmission period BUSY Command sequence execution period DTBUSY_TU DTBUSY Figure 19.4 Example of Command Sequence for Commands without Data Transfer...
Page 715: Figure 19.5 Example Of Command Sequence For Commands Without Data Transfer (With Data Busy State)
Section 19 Multimedia Card Interface (MCIF) MCCLK Command response reception Command output (48 bits) MCCMD MCDAT (Busy state) (CMDSTRT) Command transmission Response reception started completed START Busy state completed (INTSTR0) CMDI CRPI DBSYI (CSTR) CWRE Command transmission period BUSY Command sequence execution period DTBUSY_TU DTBUSY Data busy period...
Page 716: Figure 19.6 Operational Flow For Commands Without Data Transfer
Section 19 Multimedia Card Interface (MCIF) Command sequence start Set command data to CMDR0 to CMDR4 Set command type to CMDTYR Set command response type to RSPTYR Set the START bit in CMDSTRT to 1 Is CRPI interrupt detected? Is CTERI or CRCERI interrupt detected? Not Busy...
Page 717: Commands With Read Data
Section 19 Multimedia Card Interface (MCIF) 19.5.5 Commands with Read Data Commands involving read data confirm the MMC status by the command arguments and command responses, and then receive MMC information and flash memory data from the MCDAT pin. The number of bytes of flash memory to be read is a block size specified by CMD16, or if not specified, reading is continued until it is aborted by CMD12M in multiblock transfer and stream transfer.
Page 718: Figure 19.7 Example Of Command Sequence For Commands With Read Data (1)
Section 19 Multimedia Card Interface (MCIF) Single block data read (Block size ≤ receive data FIFO size) MCCLK CMD17 (READ_SINGLE_BLOCK) MCCMD Command response Command MCDAT Read data Command (CMDSTRT) transmission started START (OPCR) RD_CONTI CMDOFF (INTSTR0) CMDI CRPI (CSTR) CWRE BUSY Single-block read command execution sequence FIFO_FULL...
Page 719: Figure 19.8 Example Of Command Sequence For Commands With Read Data (2)
Section 19 Multimedia Card Interface (MCIF) Single block data read (Block size > receive data FIFO size) MCCLK Transfer clock transmission Transfer clock transmission CMD17 (READ_SINGLE_BLOCK) halted resumed MCCMD Command response Command Block data reception Block data reception suspended resumed MCDAT Read data Read data...
Page 720: Figure 19.9 Example Of Command Sequence For Commands With Read Data (3)
Section 19 Multimedia Card Interface (MCIF) Figure 19.9 Example of Command Sequence for Commands with Read Data (3) Rev. 3.00 Jan 25, 2006 page 666 of 872 REJ09B0286-0300...
Page 721: Figure 19.10 Example Of Command Sequence For Commands With Read Data (4)
Section 19 Multimedia Card Interface (MCIF) Figure 19.10 Example of Command Sequence for Commands with Read Data (4) Rev. 3.00 Jan 25, 2006 page 667 of 872 REJ09B0286-0300...
Page 722: Figure 19.11 Operational Flow For Commands With Read Data
Section 19 Multimedia Card Interface (MCIF) Command sequence start : Set block length Execute CMD16 Set the number of transfer bytes (block size) to TBCR : Execute multiblock data read Execute CMD18M Is CTERI or CRCERI interrupt detected? Is CRPI interrupt detected? Read response register Error...
Page 723: Commands With Write Data
Section 19 Multimedia Card Interface (MCIF) 19.5.6 Commands with Write Data Commands involving write data confirm the MMC status by the command responses after command transmission, and then transmit MMC information and flash memory data from the MCDAT pin. For a command that is related to time-consuming processing such as flash memory write, the MMC indicates the data busy state via the DAT pin.
Page 724: Figure 19.12 Example Of Command Sequence For Commands With Write Data (1)
Section 19 Multimedia Card Interface (MCIF) sequence is detected by poling the BUSY flag in CSTR, the data transfer end interrupt (DTI), or the data response end interrupt (DPRI). • The end of the data busy state is detected by poling the DTBUSY flag in CSTR or by the data busy end interrupt (DBSYI).
Page 725: Figure 19.13 Example Of Command Sequence For Commands With Write Data (2)
Section 19 Multimedia Card Interface (MCIF) Single-block data write (Block size > Transmit data FIFO size) MCCLK Transfer clock Transfer clock CMD24 (WRITE_SINGLE_BLOCK) transmission halted transmission resumed MCCMD Command Command response Status MCDAT Write data Write data Busy Command transmission started Block data Block data (CMDSTRT)
Page 726: Figure 19.14 Example Of Command Sequence For Commands With Write Data (3)
Section 19 Multimedia Card Interface (MCIF) Figure 19.14 Example of Command Sequence for Commands with Write Data (3) Rev. 3.00 Jan 25, 2006 page 672 of 872 REJ09B0286-0300...
Page 727: Figure 19.15 Example Of Command Sequence For Commands With Write Data (4)
Section 19 Multimedia Card Interface (MCIF) Figure 19.15 Example of Command Sequence for Commands with Write Data (4) Rev. 3.00 Jan 25, 2006 page 673 of 872 REJ09B0286-0300...
Page 728: Figure 19.16 Operational Flow For Commands With Write Data
Section 19 Multimedia Card Interface (MCIF) Command sequence start : Set block length Execute CMD16 Set the number of transfer bytes (block size) to TBCR : Execute multiblock data write Execute CMD25M Is CTERI or CRCERI interrupt detected? Is CRPI interrupt detected? Read response register Error...
Page 729: Operations In Spi Mode
Section 19 Multimedia Card Interface (MCIF) 19.6 Operations in SPI Mode SPI mode is an operating mode in which the transfer clock is output from the MCCLK pin, and command/response/data is input/output via the MCRxD pin and MCTxD pin. In SPI mode, one of multiple MMCs is selected by the chip select (CS) pin. Therefore, card selection using broadcast commands for MMC mode is not supported.
Page 730: Figure 19.17 Example Of Command Sequence For Commands Without Data Transfer
Section 19 Multimedia Card Interface (MCIF) MCCLK MCTxD Command output (48 bits) Command transmission ended (No busy state) MCRxD Command response reception Response reception ended MCCSA Command transmission started (CMDSTRT) START (INTSTR0) CMDI CRPI DBSYI (CSTR) CWRE Command transmission period BUSY Command sequence execution period DTBUSY_TU...
Page 731: Figure 19.18 Example Of Command Sequence For Commands Without Data Transfer (With Data Busy State)
Section 19 Multimedia Card Interface (MCIF) MCCLK MCTxD Command output (48 bits) Command transmission ended Command response completed Command response reception MCRxD (Busy state) Response reception ended MCCSA Command transmission started (CMDSTRT) START (INTSTR0) CMDI CRPI DBSYI (CSTR) CWRE Command transmission period BUSY Command sequence execution period DTBUSY_TU...
Page 732: Figure 19.19 Operational Flow For Commands Without Data Transfer
Section 19 Multimedia Card Interface (MCIF) Command sequence start Set command data to CMDR0 to CMDR4 Set command type to CMDTYR Set command response type to RSPTYR Set the START bit in CMDSTRT to 1 Is CRPI interrupt detected? Is CTERI interrupt detected? Not Busy Is data busy state...
Page 733: Commands With Read Data
Section 19 Multimedia Card Interface (MCIF) 19.6.2 Commands with Read Data Commands with read data confirm the MMC status by the command responses, and then receive MMC information and flash memory data. The number of bytes of flash memory to be read is a block size specified by CMD16. When block size >...
Page 734: Figure 19.20 Example Of Command Sequence For Commands With Read Data (1)
Section 19 Multimedia Card Interface (MCIF) MCCLK CMD17 (READ_SINGLE_BLOCK) MCDWR Command MCDRD Command response Read data MCCSA Command transmission (CMDSTRT) started START (OPCR) RD_CONTI CMDOFF (IINTSTR0) CMDI CRPI (CSTR) CWRE BUSY Single-block read command execution sequence FIFO_FULL Figure 19.20 Example of Command Sequence for Commands with Read Data (1) Rev.
Page 735: Figure 19.21 Example Of Command Sequence For Commands With Read Data (2)
Section 19 Multimedia Card Interface (MCIF) MCCLK Transfer clock Transfer clock CMD17 (READ_SINGLE_BLOCK) transmission halted transmission resumed MCDWR Block data Block data Command reception resumed reception suspended MCDRD Command response Read data Read data MCCSA Command (CMDSTRT) transmission started START (OPCR) RD_CONTI CMDOFF...
Page 736: Figure 19.22 Operational Flow For Commands With Read Data
Section 19 Multimedia Card Interface (MCIF) Command sequence start Set the number of transfer bytes (block size) to TBCR Execute CMD16 : Set block length : Execute single-block data read Execute CMD17 Is CTERI interrupt detected? Is CRPI interrupt detected? Read response register Error Response...
Page 737: Commands With Write Data
Section 19 Multimedia Card Interface (MCIF) 19.6.3 Commands with Write Data Commands with write data confirm the MMC status by the command responses, and then transmit MMC information and flash memory data. For a command that is related to time-consuming processing such as flash memory write, the MMC indicates the data busy state.
Page 738: Figure 19.23 Example Of Command Sequence For Commands With Write Data (1)
Section 19 Multimedia Card Interface (MCIF) MCCLK CMD24 (WRITE_SINGLE_BLOCK) MCDWR Command Write data Data response Command response MCDRD Busy MCCSA Command (CMDSTRT) transmission started START (OPCR) DATAEN CMDOFF (IINTSTR0) CMDI CRPI DRPI DBSYI (CSTR) CWRE BUSY Single-block write command execution sequence FIFO_EMPTY DTBUSY DTBUSY_TU...
Page 739: Figure 19.24 Example Of Command Sequence For Commands With Write Data (2)
Section 19 Multimedia Card Interface (MCIF) MCCLK Transfer clock Transfer clock CMD24 (WRITE_SINGLE_BLOCK) transmission halted transmission resumed MCDWR Write data Write data Command Data response MCDRD Command response Busy Block data Block data transmission transmission suspended resumed MCCSA Command (CMDSTRT) transmission started START...
Page 740: Figure 19.25 Operational Flow For Commands With Write Data
Section 19 Multimedia Card Interface (MCIF) Command sequence start Set the number of transfer bytes (block size) to TBCR : Set block length Execute CMD16 : Execute single-block data write Execute CMD24 Is CTERI interrupt detected? Is CRPI interrupt detected? Read response register Error Response...
Page 741: Interrupt Sources
Section 19 Multimedia Card Interface (MCIF) 19.7 Interrupt Sources Table 19.6 lists the MCIF interrupt sources. The interrupt sources are classified into three groups, each to which an interrupt vector is assigned. Each interrupt source can be individually enabled by the enable bits in INTCR0 and INTCR1.
Page 742 Section 19 Multimedia Card Interface (MCIF) Rev. 3.00 Jan 25, 2006 page 688 of 872 REJ09B0286-0300...
Page 743: Section 20 Encryption Operation Circuit (Des And Gf)
Section 20 Encryption Operation Circuit (DES and GF) Section 20 Encryption Operation Circuit (DES and GF) This section will be made available on conclusion of a nondisclosure agreement. For details, contact your Renesas sales agency. Rev. 3.00 Jan 25, 2006 page 689 of 872 DESGE00A_000020020300...
Page 744 Section 20 Encryption Operation Circuit (DES and GF) Rev. 3.00 Jan 25, 2006 page 690 of 872 REJ09B0286-0300...
Page 745: Section 21 D/A Converter
Section 21 D/A Converter Section 21 D/A Converter 21.1 Features • 8-bit resolution • Two output channels • Conversion time: Max. 10 µs (when load capacitance is 20 pF) • Output voltage: 0 V to AV • D/A output retaining function in software standby mode Module data bus Internal data bus AVref...
Page 746: Input/Output Pins
Section 21 D/A Converter 21.2 Input/Output Pins Table 21.1 summarizes the input/output pins used by the D/A converter. Table 21.1 Pin Configuration Pin Name Symbol Function Analog power supply pin AVCC Input Analog block power supply Analog ground pin AVSS Input Analog block ground and reference voltage Analog output pin 0...
Page 747: Table 21.2 D/A Channel Enable
Section 21 D/A Converter Bit Name Initial Value Description DAOE1 D/A Output Enable 1 Controls D/A conversion and analog output. 0: Analog output DA1 is disabled 1: D/A conversion for channel 1 and analog output DA1 are enabled DAOE0 D/A Output Enable 0 Controls D/A conversion and analog output.
Page 748: Operation
Section 21 D/A Converter 21.4 Operation The D/A converter incorporates two channels of the D/A circuits and can be converted individually. When the DAOE bit in DACR is set to 1, D/A conversion is enabled and conversion results are output. An example of D/A conversion of channel 0 is shown below.
Page 749: Usage Notes
Section 21 D/A Converter 21.5 Usage Notes 1. When this LSI enters software standby mode with D/A conversion enabled, the D/A output is retained, and the analog power supply current is equal to as during D/A conversion. If the analog power supply current needs to be reduced in software standby mode, clear the DAOE1, DAOE0, and DAE bits all to 0 to disable D/A output.
Page 750 Section 21 D/A Converter Rev. 3.00 Jan 25, 2006 page 696 of 872 REJ09B0286-0300...
Page 751: Section 22 A/D Converter
Section 22 A/D Converter Section 22 A/D Converter This LSI includes a successive-approximation-type 10-bit A/D converter that allows up to six analog input channels and up to eight digital input channels to be selected. A/D conversion for digital input is effective as a comparator in multiple input testing. 22.1 Features •...
Page 752: Figure 22.1 Block Diagram Of A/D Converter
Section 22 A/D Converter Module data bus Internal data bus AVCC AVref 10-bit D/A AVSS φ/8 Comparator Control circuit φ/16 Sample-and-hold circuit CIN0 to CIN7 ADI interrupt signal Conversion start trigger from 8-bit timer ADTRG Legend: ADCR : A/D control register ADCSR : A/D control/status register ADDRA : A/D data register A ADDRB : A/D data register B...
Page 753: Input/Output Pins
Section 22 A/D Converter 22.2 Input/Output Pins Table 22.1 summarizes the pins used by the A/D converter. The 8 analog input pins are divided into two groups consisting of four channels. Analog input pins 0 to 3 (AN0 to AN3) comprising group 0 and analog input pins 4 to 7 (AN4 to AN7) comprising group1.
Page 754: Register Descriptions
Section 22 A/D Converter 22.3 Register Descriptions The A/D converter has the following registers. • A/D data register A (ADDRA) • A/D data register B (ADDRB) • A/D data register C (ADDRC) • A/D data register D (ADDRD) • A/D control/status register (ADCSR) •...
Page 755: A/D Control/Status Register (Adcsr)
Section 22 A/D Converter 22.3.2 A/D Control/Status Register (ADCSR) ADCSR controls A/D conversion operations. Bit Name Initial Value Description R/(W) * A/D End Flag A status flag that indicates the end of A/D conversion. [Setting conditions] • When A/D conversion ends in single mode •...
Page 756: A/D Control Register (Adcr)
Section 22 A/D Converter Bit Name Initial Value Description Channel Select 2 to 0 Select analog input channels. When SCAN = 0 When SCAN = 1 000: CIN0 to CIN7 000: CIN0 to CIN7 001: Setting prohibited 001: Setting prohibited 010: AN2 010: Setting prohibited 011: AN3...
Page 757: Keyboard Comparator Control Register (Kbcomp)
Section 22 A/D Converter 22.3.4 Keyboard Comparator Control Register (KBCOMP) KBCOMP selects the CIN input channel for which A/D conversion is performed and enables or disables the comparator scan function of CIN7 to CIN0. The DTC decides where to store the A/D conversion result according to settings of the KBCH2 to KBCH0 bits.
Page 758: Dtc Comparator Scan
Section 22 A/D Converter 22.4 DTC Comparator Scan The DTC should be set as shown in table 22.3 to scan CIN7 to CIN0 using the DTC comparator scan function. Table 22.3 CIN7 to CIN0 Scan by DTC Comparator Scan Function Register Bit Name Description...
Page 759: Operation
Section 22 A/D Converter The A/D converter repeats A/D conversion of input channel 0 according to the settings of ADCSR and ADCR. Input channel 0 is connected to CIN7 to CIN0. The KBCH2 to KBCH0 bits in KBCOMP select one channel among CIN7 to CIN0. The KBCH2 to KBCH0 bits are automatically incremented by the DTC when the SCANE bit is set to 1.
Page 760: Scan Mode
Section 22 A/D Converter 22.5.2 Scan Mode In scan mode, A/D conversion is to be performed sequentially on the specified channels (four channels max.). Operations are as follows. 1. When the ADST bit in ADCSR is set to 1 by software or an external trigger input, A/D conversion starts on the first channel in the group (CIN0 when the CH2 bit in ADCSR is 0 while the SCANE and KBADE bits in KBCOMP are B'11, or AN4 when the CH2 bit in ADCSR is 1).
Page 761: Figure 22.2 A/D Conversion Timing
Section 22 A/D Converter φ Address Write signal Input sampling timing CONV Legend: : ADCSR write cycle : ADCSR address : A/D conversion start delay : Input sampling time : A/D conversion time CONV Figure 22.2 A/D Conversion Timing Table 22.4 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Item...
Page 762: External Trigger Input Timing
Section 22 A/D Converter 22.5.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to B'11 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion.
Page 763: A/D Conversion Accuracy Definitions
Section 22 A/D Converter 22.7 A/D Conversion Accuracy Definitions This LSI’s A/D conversion accuracy definitions are given below. • Resolution The number of A/D converter digital output codes • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 22.4). •...
Page 764: Figure 22.4 A/D Conversion Accuracy Definitions
Section 22 A/D Converter Digital output Ideal A/D conversion characteristic Quantization error 1022 1023 1024 1024 1024 1024 Analog input voltage Figure 22.4 A/D Conversion Accuracy Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Analog Offset error...
Page 765: Usage Notes
Section 22 A/D Converter 22.8 Usage Notes 22.8.1 Permissible Signal Source Impedance This LSI’s analog input is designed so that the conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 kΩ or less. This specification is provided to enable the A/D converter’s sample-and-hold circuit input capacitance to be charged within the sampling time;...
Page 766: Setting Range Of Analog Power Supply And Other Pins
Section 22 A/D Converter 22.8.3 Setting Range of Analog Power Supply and Other Pins If conditions shown below are not met, the reliability of this LSI may be adversely affected. • Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range ≤...
Page 767: Figure 22.7 Example Of Analog Input Protection Circuit
Section 22 A/D Converter If a filter capacitor is connected, the input currents at the analog input pins (AN2 to AN7) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (R ), an error will arise in the analog input pin voltage.
Page 768 Section 22 A/D Converter Rev. 3.00 Jan 25, 2006 page 714 of 872 REJ09B0286-0300...
Page 769: Section 23 Ram
Section 23 RAM Section 23 RAM This LSI has 10 kbytes of on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR).
Page 770 Section 23 RAM Rev. 3.00 Jan 25, 2006 page 716 of 872 REJ09B0286-0300...
Page 771: Section 24 Rom
Section 24 ROM Section 24 ROM This LSI has an on-chip flash memory. The features of the flash memory are summarized below. A block diagram of the flash memory is shown in figure 24.1. 24.1 Features • Size: 256 kbytes •...
Page 772: Mode Transition Diagrams
Section 24 ROM Internal address bus Internal data bus (16 bits) FLMCR1 FLMCR2 Operating Bus interface/controller Mode pin mode EBR1 EBR2 Flash memory (256 kbytes) Legend: FLMCR1 : Flash memory control register 1 FLMCR2 : Flash memory control register 2 EBR1 : Erase block register 1 EBR2...
Page 773: Figure 24.2 Flash Memory State Transitions
Section 24 ROM Reset state User mode (on-chip ROM enabled) FLSHE = 0 → FWE → FLSHE = 1 Programmer mode User program mode Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory.
Page 774: Figure 24.3 Boot Mode
Section 24 ROM 1. Initial state 2. SCI communication check The flash memory is erased at shipment. When boot mode is entered, the boot program in The following describes how to write over this LSI (originally incorporated in the chip) is started an old-version application program or data in and SCI communication is checked.
Page 775: Figure 24.4 User Program Mode (Example)
Section 24 ROM 1. Initial state 2. Programming/erase control program transfer (1) The program that will transfer the programming/erase The transfer program in the flash memory is executed and control program from flash memory to on-chip RAM the programming/erase control program is transferred to RAM. should be written into the flash memory by the user beforehand.
Page 776: Block Configuration
Section 24 ROM 24.3 Block Configuration Figure 24.5 shows the block configuration of 256-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The flash memory is divided into 64 kbytes (3 blocks), 32 kbytes (1 block), and 4 kbytes (8 blocks). Erasing is performed in these divided units.
Page 777: Input/Output Pins
Section 24 ROM 24.4 Input/Output Pins The flash memory is controlled by means of the pins shown in table 24.2. Table 24.2 Pin Configuration Pin Name Function Input Reset Input Sets this LSI’s operating mode Input Sets this LSI’s operating mode Input Sets this LSI’s operating mode Input...
Page 778 Section 24 ROM Bit Name Initial Value Description Flash Write Enable Used to monitor the FWE pin state. When this bit is cleared to 0, flash memory write or erasure is protected by hardware. When this bit is set to 1, hardware protect is cancelled and the SWE bit can be read from or written to.
Page 779: Flash Memory Control Register 2 (Flmcr2)
Section 24 ROM 24.5.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 monitors the state of flash memory programming/erasing protection (error protection) and sets up the flash memory to transit to programming/erasing mode. FLMCR2 is initialized to H'00 by a reset or in hardware standby mode. The ESU and PSU bits are cleared to 0 in software standby mode, sub-active mode, sub-sleep mode, or watch mode, or when the SWE bit in FLMCR1 is cleared to 0.
Page 780 Section 24 ROM EBR1 Bit Name Initial Value Description 7 to 4 — All 0 R/(W) Reserved The initial value should not be changed. R/W * EB11 When this bit is set to 1, 64 kbytes of EB11 (H'030000 to H'03FFFF) are to be erased. R/W * EB10 When this bit is set to 1, 64 kbytes of EB10...
Page 781: Operating Modes
Section 24 ROM 24.6 Operating Modes The flash memory is connected to the CPU via a 16-bit data bus, enabling byte data and word data to be accessed in a single state. Even addresses are connected to the upper 8 bits and odd addresses are connected to the lower 8 bits.
Page 782: Boot Mode
Section 24 ROM 24.7.1 Boot Mode Table 24.5 shows the boot mode operations between reset end and branching to the programming control program. 1. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 24.8, Flash Memory Programming/Erasing.
Page 783 Section 24 ROM branching to the programming control program. These registers must be initialized at the beginning of the programming control program, since the stack pointer (SP), in particular, is used implicitly in subroutine calls, etc. 7. Boot mode can be cleared by a reset. Cancel the reset * after driving the reset pin low, waiting at least 20 states, and then setting the mode pins.
Page 784: Table 24.5 Boot Mode Operation
Section 24 ROM Table 24.5 Boot Mode Operation Host Operation Communications Contents LSI Operation Processing Contents Processing Contents Branches to boot program at reset-start. Boot program start H'00, H'00 . . . H'00 Continuously transmits data H'00 • Measures low-level period of receive data H'00. at specified bit rate.
Page 785: Figure 24.6 On-Chip Ram Area In Boot Mode
Section 24 ROM Table 24.6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate Is Possible Host Bit Rate System Clock Frequency Range of LSI 19200 bps 8 to 25 MHz 9600 bps 5 to 25 MHz 4800 bps 5 to 25 MHz H'FF0800 ID code area...
Page 786: User Program Mode
Section 24 ROM 24.7.2 User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must set branching conditions and provide on-board means of supplying programming data. The flash memory must contain the user program/erase control program or a program which provides the user program/erase control program from external memory.
Page 787: Program/Program-Verify
Section 24 ROM accordance with the descriptions in section 24.8.1, Program/Program-Verify and section 24.8.2, Erase/Erase-Verify, respectively. 24.8.1 Program/Program-Verify When writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 24.9 should be followed. Performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting this LSI to voltage stress or sacrificing program data reliability.
Page 788: Figure 24.9 Program/Program-Verify Flowchart
Section 24 ROM Write pulse application subroutine Start of programming Perform programming in the erased state. Sub-Routine Write Pulse START Do not perform additional programming on previously programmed addresses. Set SWE bit in FLMCR1 WDT enable Wait (x) µs Set PSU bit in FLMCR2 Store 128-byte program data in program Wait (γ) µs data area and reprogram data area...
Page 789: Erase/Erase-Verify
Section 24 ROM 24.8.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 24.10 should be followed. 1. Prewriting (setting erase block data to all 0) is not necessary. 2. Erasing is performed in block units. Make only a single-block specification in erase block registers 1 and 2 (EBR1 and EBR2).
Page 790: Figure 24.10 Erase/Erase-Verify Flowchart
Section 24 ROM START Set SWE bit in FLMCR1 Wait ( x ) µs n = 1 Set EBR1 and EBR2 Enable WDT Set ESU bit in FLMCR2 Wait ( y ) µs Start of erasing Set E bit in FLMCR1 Wait ( z ) ms End of erasing Clear E bit in FLMCR1...
Page 791: Program/Erase Protection
Section 24 ROM 24.9 Program/Erase Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 24.9.1 Hardware Protection Hardware protection is a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a low level input to the FEW pin, by a reset (including WDT overflow reset), or a transition to hardware standby mode, software standby mode, sub-active mode, sub- sleep mode, or watch mode.
Page 792: Interrupts During Flash Memory Programming/Erasing
In programmer mode, the on-chip flash memory can be programmed/erased by a PROM programmer via a socket adapter, just like for a discrete flash memory. Use a PROM programmer that supports the Renesas 256-kbyte flash memory on-chip MCU device. Figure 24.11 shows a memory map in programmer mode.
Page 793: Usage Notes
If a voltage higher than the rated voltage is applied, the product may be fatally damaged. Use a PROM programmer that supports the Renesas 256-kbyte flash memory on-chip MCU device at 3.3 V. Do not set the programmer to HN28F101 or the programming voltage to 5.0 V. Use only the specified socket adapter.
Page 794 Section 24 ROM 6. Do not perform additional programming. Programming must be performed in the erased state. Program the area with 128-byte programming-unit blocks in on-board programming or programmer mode only once. Perform programming in the state where the programming-unit block is fully erased. 7.
Page 795: Section 25 User Debug Interface (H-Udi)
Section 25 User Debug Interface (H-UDI) Section 25 User Debug Interface (H-UDI) The user debug interface (H-UDI) provides a boundary scan function using the JTAG (Joint Test Action Group, IEEE Std 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture) and a pin-compatible serial interface. The H-UDI performs serial transfer by means of external signal control.
Page 796: Figure 25.1 Block Diagram Of H-Udi
Section 25 User Debug Interface (H-UDI) ETCK ETMS controller Decoder ETRST ETDI SDIR SDIDR ETDO Legend: SDIR: Instruction register SDBPR: Bypass register SDBSR: Boundary scan register SDIDR: ID code register Figure 25.1 Block Diagram of H-UDI Rev. 3.00 Jan 25, 2006 page 742 of 872 REJ09B0286-0300...
Page 797: Input/Output Pins
Section 25 User Debug Interface (H-UDI) 25.2 Input/Output Pins Table 25.1 shows the H-UDI pin configuration. Table 25.1 Pin Configuration Pin Name Abbreviation Function Test clock ETCK Input Test clock input Provides an independent clock supply to the H- UDI. As the clock input to the ETCK pin is supplied directly to the H-UDI, a clock waveform with a duty cycle close to 50% should be input.
Page 798: Register Descriptions
Section 25 User Debug Interface (H-UDI) 25.3 Register Descriptions The H-UDI has the following registers. • Instruction register (SDIR) • Bypass register (SDBPR) • Boundary scan register (SDBSR) • ID code register (SDIDR) Instructions can be input to the instruction register (SDIR) by serial transfer from the test data input pin (ETDI).
Page 799 Section 25 User Debug Interface (H-UDI) Bit Name Initial Value Description Test Set Bits 0000: EXTEST mode 0001: Setting prohibited 0010: CLAMP mode 0011: HIGHZ mode 0100: SAMPLE/PRELOAD mode 0101: Setting prohibited 1101: Setting prohibited 1110: IDCODE mode (Initial value) 1111: BYPASS mode ...
Page 800: Bypass Register (Sdbpr)
Section 25 User Debug Interface (H-UDI) 25.3.2 Bypass Register (SDBPR) SDBPR is a 1-bit shift register. In BYPASS, CLAMP, or HIGHZ mode, SDBPR is connected between the ETDI and ETDO pins. 25.3.3 Boundary Scan Register (SDBSR) SDBSR is a shift register provided on the PAD for controlling the I/O terminals of this LSI. Using EXTEST mode or SAMPLE/PRELOAD mode, a boundary scan test conforming to the IEEE1149.1 standard can be performed.
Page 801: Table 25.3 Correspondence Between Pins And Boundary Scan Register
Section 25 User Debug Interface (H-UDI) Table 25.3 Correspondence between Pins and Boundary Scan Register Pin No. Pin Name Input/Output Bit No. from ETDI Input Input Input Input Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output...
Page 802 Section 25 User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output...
Page 803 Section 25 User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. Input Enable Output Input Enable Output USDP Input Enable * Output USDM Input Enable * Output Input Input Input Input Input Input Input Enable Output Input Enable Output Input Enable...
Page 804 Section 25 User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output...
Page 805 Section 25 User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output...
Page 806 Section 25 User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output...
Page 807 Section 25 User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output...
Page 808: Id Code Register (Sdidr)
Section 25 User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. Input Enable Output Input Enable Output Input to ETDO Notes: The enable signals are active-high. When an enable signal is driven high, the corresponding pin is driven with the output value. * If either the enable signal for the USDP pin or that for the USDM pin is driven high, both pins are driven by the output values.
Page 809: Operation
Section 25 User Debug Interface (H-UDI) 25.4 Operation 25.4.1 TAP Controller State Transitions Figure 25.2 shows the internal states of the TAP controller. State transitions basically conform to the IEEE1149.1 standard. Tset -Logic-Reset Run-Test/Idle Select-DR-Scan Select-IR-Scan Capture-DR Capture-IR Shift-DR Shift-IR Exit1-DR Exit1-IR Pause-DR...
Page 810: Boundary Scan
Section 25 User Debug Interface (H-UDI) 25.5 Boundary Scan The H-UDI pins can be placed in the boundary scan mode stipulated by the IEEE1149.1 standard by setting a command in SDIR. 25.5.1 Supported Instructions This LSI supports the three essential instructions defined in the IEEE1149.1 standard (BYPASS, SAMPLE/PRELOAD, and EXTEST) and optional instructions (CLAMP, HIGHZ, and IDCODE).
Page 811: Notes
Section 25 User Debug Interface (H-UDI) Data loaded into the output pin boundary scan register in the Capture-DR state is not used for external circuit testing (it is replaced by a shift operation). • CLAMP [Instruction code: B'0010] When the CLAMP instruction is enabled, the output pin outputs the value of the boundary scan register that has been previously set by the SAMPLE/PRELOAD instruction.
Page 812: Usage Notes
Section 25 User Debug Interface (H-UDI) 25.6 Usage Notes 1. A reset must always be executed by driving the ETRST pin to 0, regardless of whether or not the H-UDI is to be activated. The ETRST pin must be held low for 20 ETCK clock cycles. For details, see section 29, Electrical Characteristics.
Page 813: Figure 25.4 Serial Data Input/Output (1)
Section 25 User Debug Interface (H-UDI) 8. If a pin with a pull-up function is sampled while its pull-up function is enabled, 1 can be detected at the corresponding input scan register. In this case, the corresponding enable scan register should be cleared to 0. 9.
Page 814: Figure 25.4 Serial Data Input/Output (2)
Section 25 User Debug Interface (H-UDI) SDIDR serial data input/output SDIDR is captured into the shift register in Capture-DR in IDCODE mode, and bits 0 to 31 of SDIDR are output in that order from the ETDO pin in Shift-DR. Data input from the ETDI pin is written to any register in Update-DR.
Page 815: Section 26 Clock Pulse Generator
Section 26 Clock Pulse Generator Section 26 Clock Pulse Generator This LSI incorporates a clock pulse generator which generates the system clock (φ), internal clock, bus master clock, and subclock (φSUB). The clock pulse generator consists of an oscillator, duty correction circuit, system clock select circuit, medium-speed clock divider, bus master clock select circuit, subclock input circuit, and waveform forming circuit.
Page 816: Oscillator
Section 26 Clock Pulse Generator The subclock input is controlled by software according to the EXCLE bit setting in the low power control register. For details on the low power control register, see section 27.1.2, Low-Power Control Register (LPWRCR). 26.1 Oscillator Clock pulses can be supplied either by connecting a crystal resonator or by providing external clock input.
Page 817: External Clock Input Method
Section 26 Clock Pulse Generator Table 26.2 Crystal Resonator Parameters Frequency(MHz) (max) (Ω Ω Ω Ω ) (max) (pF) 26.1.2 External Clock Input Method Figure 26.4 shows a typical method of connecting an external clock signal. To leave the XTAL pin open, incidental capacitance should be 10 pF or less.
Page 818: Figure 26.5 External Clock Input Timing
Section 26 Clock Pulse Generator Table 26.3 External Clock Input Conditions VCC = 3.0 to 3.6 V VCC = 2.7 to 3.6 V Test Item Symbol Unit Conditions External clock — — Figure 26.5 input pulse width low level External clock —...
Page 819: Duty Correction Circuit
Section 26 Clock Pulse Generator Table 26.4 External Clock Output Stabilization Delay Time Condition: V = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = AV = 0 V Item Symbol Min. Max. Unit Remarks µs External clock output stabilization delay —...
Page 820: Medium-Speed Clock Divider
Section 26 Clock Pulse Generator 26.3 Medium-Speed Clock Divider The medium-speed clock divider divides the system clock (φ), and generates φ/2, φ/4, φ/8, φ/16, and φ/32 clocks. 26.4 Bus Master Clock Select Circuit The bus master clock select circuit selects a clock to supply the bus master with either the system clock (φ) or medium-speed clock (φ/2, φ/4, φ/8, φ/16, or φ/32) by the SCK2 to SCK0 bits in SBYCR.
Page 821: Waveform Forming Circuit
Section 26 Clock Pulse Generator EXCLH EXCLL × 0.5 EXCL EXCLr EXCLf Figure 26.7 Subclock Input Timing 26.6 Waveform Forming Circuit To remove noise from the subclock input at the EXCL pin, the subclock is sampled by a divided φ clock.
Page 822: Usage Notes
Section 26 Clock Pulse Generator of the PLL circuit output clock. For details, see section 18.3.17, USB PLL Control Register (UPLLCR). The 24-MHz clock generated by the PLL circuit can also be used as the system clock. For details, see section 27.1.3, System Control Register 2 (SYSCR2). To activate the PLL circuit, first clear the SMSTPB1 bit in SUBMSTPBL to 0, then after clearing the USB module stop mode, make settings for UPLLCR.
Page 823: Processing For X1 And X2 Pins
Section 26 Clock Pulse Generator 26.9.3 Processing for X1 and X2 Pins The X1 and X2 pins should be left open as shown in figure 26.9. Open Open Figure 26.9 Processing for X1 and X2 Pins Rev. 3.00 Jan 25, 2006 page 769 of 872 REJ09B0286-0300...
Page 824 Section 26 Clock Pulse Generator Rev. 3.00 Jan 25, 2006 page 770 of 872 REJ09B0286-0300...
Page 825: Section 27 Power-Down Modes
Section 27 Power-Down Modes Section 27 Power-Down Modes For operating modes after the reset state is cancelled, this LSI has not only the normal program execution state but also seven power-down modes in which power consumption is significantly reduced. In addition, there is also module stop mode in which reduced power consumption can be achieved by individually stopping on-chip peripheral modules.
Page 826: Register Descriptions
Section 27 Power-Down Modes 27.1 Register Descriptions Power-down modes are controlled by the following registers. To access SBYCR, LPWRCR, SYSCR2, MSTPCRH, and MSTPCRL, the FLSHE bit in the serial timer control register (STCR) must be cleared to 0. For details on STCR, see section 3.2.3, Serial Timer Control Register (STCR).
Page 827 Section 27 Power-Down Modes Bit Name Initial Value R/W Description STS2 Standby Timer Select 2 to 0 STS1 Select the wait time for clock stabilization from clock oscillation start when canceling software standby mode, STS0 watch mode, or subactive mode. Select a wait time of 8 ms (oscillation stabilization time) or more, depending on the operating frequency.
Page 828: Low-Power Control Register (Lpwrcr)
Section 27 Power-Down Modes Table 27.1 Operating Frequency and Wait Time STS2 STS1 STS0 Wait Time 24M Hz 20 MHz 10 MHz 8 MHz 6 MHz Unit 8192 states 16384 states 32768 states 65536 states 10.9 131072 states 13.1 16.4 21.8 262144 states 10.9...
Page 829: System Control Register 2 (Syscr2)
Section 27 Power-Down Modes Bit Name Initial Value R/W Description LSON Low-Speed On Flag Specifies the operating mode to be entered after executing the SLEEP instruction. This bit also controls whether to shift to high-speed mode or subactive mode when watch mode is cancelled.
Page 830 Section 27 Power-Down Modes Before using this function to switch the clock, the PLL circuit must be started up to provide a stable 24-MHz clock. Bit Name Initial Value Description KWUL1 For details on bits 7 to 5, see section 9.6.4, System Control Register 2 (SYSCR2).
Page 831: Module Stop Control Registers H And L (Mstpcrh, Mstpcrl) Sub-Chip Module Stop Control Registers Bh And Bl (Submstpbh, Submstpbl)
Section 27 Power-Down Modes 27.1.4 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL) Sub-Chip Module Stop Control Registers BH and BL (SUBMSTPBH, SUBMSTPBL) MSTPCR and SUBMSTPB specify on-chip peripheral modules to shift to module stop mode in module units. Each module can enter module stop mode by setting the corresponding bit to 1. •...
Page 832: Mode Transitions And Lsi States
Section 27 Power-Down Modes • SUBMSTPBH Bit Name Initial Value R/W Corresponding Module SMSTPB15 SMSTPB14 SMSTPB13 SMSTPB12 SMSTPB11 SMSTPB10 SMSTPB9 Encryption operation circuit (GF) SMSTPB8 Encryption operation circuit (DES) Note: * Do not clear this bit to 0. • SUBMSTPBL Bit Name Initial Value R/W Corresponding Module...
Page 833: Figure 27.1 Mode Transition Diagram
Section 27 Power-Down Modes Program halt state STBY pin = Low Hardware Reset state standby mode STBY pin = High RES pin = Low RES pin = High Program execution state SSBY = 0, LSON = 0 Sleep mode SLEEP instruction (main clock) High-speed mode (main clock)
Page 834: Table 27.2 Lsi Internal States In Each Operating Mode
Section 27 Power-Down Modes Table 27.2 LSI Internal States in Each Operating Mode High- Medium- Module Sub- Sub- Software Hardware Function Sleep Watch Speed Speed Stop Active Sleep Standby Standby System clock pulse Function- Function- Function- Function- Halted Halted Halted Halted Halted generator...
Page 835: Medium-Speed Mode
Section 27 Power-Down Modes 27.3 Medium-Speed Mode The CPU makes a transition to medium-speed mode as soon as the current bus cycle ends according to the setting of the SCK2 to SCK0 bits in SBYCR. In medium-speed mode, the CPU operates on the operating clock (φ/2, φ/4, φ/8, φ/16, or φ/32) specified by the SCK2 to SCK0 bits.
Page 836: Sleep Mode
Section 27 Power-Down Modes Medium-speed mode φ, peripheral module clock Bus master clock SBYCR SBYCR Internal address bus Internal write signal Figure 27.2 Medium-Speed Mode Timing 27.4 Sleep Mode The CPU makes a transition to sleep mode if the SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0 and the LSON bit in LPWRCR is cleared to 0.
Page 837 Section 27 Power-Down Modes states of on-chip peripheral modules other than the SCI, PWM, and PWMX, are retained as long as the prescribed voltage is supplied. Software standby mode is cleared by an external interrupt (NMI, IRQ15 to IRQ0, KIN9 to KIN0, or WUE15 to WUE8), the RES pin input, or STBY pin input.
Page 838: Hardware Standby Mode
Section 27 Power-Down Modes Oscillator φ NMIEG SSBY NMI exception Software standby mode NMI exception Oscillation handling (power-down mode) handling stabilization NMIEG = 1 time t SSBY = 1 OSC2 SLEEP instruction Figure 27.3 Software Standby Mode Application Example 27.6 Hardware Standby Mode The CPU makes a transition to hardware standby mode from any mode when the STBY pin is driven low.
Page 839: Watch Mode
Section 27 Power-Down Modes Figure 27.4 shows an example of hardware standby mode timing. Oscillator STBY Oscillation Reset stabilization exception time handling Figure 27.4 Hardware Standby Mode Timing 27.7 Watch Mode The CPU makes a transition to watch mode when the SLEEP instruction is executed in high-speed mode or subactive mode with the SSBY bit in SBYCR set to 1, the DTON bit in LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1.
Page 840: Subsleep Mode
Section 27 Power-Down Modes masked by the CPU. In the case of an interrupt from the on-chip peripheral modules, watch mode is not exited if the interrupt enable register has been set to disable the reception of that interrupt or the interrupt is masked by the CPU.
Page 841: Subactive Mode
Section 27 Power-Down Modes 27.9 Subactive Mode The CPU makes a transition to subactive mode when the SLEEP instruction is executed in high- speed mode with the SSBY bit in SBYCR set to 1, the DTON bit and LSON bit in LPWRCR set to 1, and the PSS bit in TCSR (WDT_1) set to 1.
Page 842: Direct Transitions
Section 27 Power-Down Modes resumes at the end of the bus cycle. In module stop mode, the internal states of modules other than the MCIF, SCI, D/A converter, A/D converter, PWM, and PWMX are retained. After the reset state is cancelled, all modules other than DTC are in module stop mode. While an on-chip peripheral module is in module stop mode, read/write access to its registers is disabled.
Page 843: Usage Notes
Section 27 Power-Down Modes 27.12 Usage Notes 27.12.1 I/O Port Status The status of the I/O ports is retained in software standby mode. Therefore, when a high level is output, the current consumption is not reduced by the amount of current to support the high level output.
Page 844 Section 27 Power-Down Modes Rev. 3.00 Jan 25, 2006 page 790 of 872 REJ09B0286-0300...
Page 845: Section 28 List Of Registers
Section 28 List of Registers Section 28 List of Registers The register list gives information on the on-chip register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below.
Page 846 Section 28 List of Registers Number Data Number Access Register Name Abbreviation of Bits Address Module Width States Command register 0 CMDR0 H'FBC0 MCIF Command register 1 CMDR1 H'FBC1 MCIF Command register 2 CMDR2 H'FBC2 MCIF Command register 3 CMDR3 H'FBC3 MCIF Command register 4...
Page 847 Section 28 List of Registers Number Data Number Access Register Name Abbreviation of Bits Address Module Width States Response register 9 RSPR9 H'FBE9 MCIF Response register 10 RSPR10 H'FBEA MCIF Response register 11 RSPR11 H'FBEB MCIF Response register 12 RSPR12 H'FBEC MCIF Response register 13...
Page 848 Section 28 List of Registers Number Data Number Access Register Name Abbreviation of Bits Address Module Width States Endpoint size register 1 EPSZR1 H'FDE4 Endpoint data register 1 EPDR1 H'FDE5 FIFO valid size register 1H FVSR1H H'FDE6 FIFO valid size register 1L FVSR1L H'FDE7 Endpoint data register 0O...
Page 849 Section 28 List of Registers Number Data Number Access Register Name Abbreviation of Bits Address Module Width States FIFO status/register/pointer 2 FSTR2 H'FEA2 FIFO status/register/pointer 3 FSTR3 H'FEA3 Data transfer control register A DTCRA H'FEA4 Data transfer control register B DTCRB H'FEA5 Data transfer ID register...
Page 850 Section 28 List of Registers Number Data Number Access Register Name Abbreviation of Bits Address Module Width States IIC operation reservation adapter ICSRA_1 H'FEB9 IIC_1 status register A_1 IIC operation reservation adapter ICSRB_1 H'FEBA IIC_1 status register B_1 IIC operation reservation adapter ICSRC_1 H'FEBB IIC_1...
Page 851 Section 28 List of Registers Number Data Number Access Register Name Abbreviation of Bits Address Module Width States DTC enable register A DTCERA H'FEEE DTC enable register B DTCERB H'FEEF DTC enable register C DTCERC H'FEF0 DTC enable register D DTCERD H'FEF1 DTC enable register E...
Page 852 Section 28 List of Registers Number Data Number Access Register Name Abbreviation of Bits Address Module Width States C bus control register_1 ICCR_1 H'FF88 IIC_1 Bit rate register_1 BRR_1 H'FF89 SCI_1 C bus status register_1 ICSR_1 H'FF89 IIC_1 Serial control register_1 SCR_1 H'FF8A SCI_1...
Page 853 Section 28 List of Registers Number Data Number Access Register Name Abbreviation of Bits Address Module Width States Input capture register CH ICRCH H'FF9C Output compare register DMH OCRDMH H'FF9C Input capture register CL ICRCL H'FF9D Output compare register DML OCRDML H'FF9D Input capture register DH...
Page 854 Section 28 List of Registers Number Data Number Access Register Name Abbreviation of Bits Address Module Width States Port 3 pull-up MOS control register P3PCR H'FFAE PORT Port 1 data direction register P1DDR H'FFB0 PORT Port 2 data direction register P2DDR H'FFB1 PORT...
Page 855 Section 28 List of Registers Number Data Number Access Register Name Abbreviation of Bits Address Module Width States Time constant register B_0 TCORB_0 H'FFCE TMR_0 Time constant register B_1 TCORB_1 H'FFCF TMR_1 Timer counter_0 TCNT_0 H'FFD0 TMR_0 Timer counter_1 TCNT_1 H'FFD1 TMR_1 PWM output enable register B...
Page 856 Section 28 List of Registers Number Data Number Access Register Name Abbreviation of Bits Address Module Width States A/D data register CH ADDRCH H'FFE4 converter A/D data register CL ADDRCL H'FFE5 converter A/D data register DH ADDRDH H'FFE6 converter A/D data register DL ADDRDL H'FFE7 converter...
Page 857 Section 28 List of Registers Number Data Number Access Register Name Abbreviation of Bits Address Module Width States Timer counter_X TCNT_X H'FFF4 TMR_X Timer counter_Y TCNT_Y H'FFF4 TMR_Y Time constant register TCORC H'FFF5 TMR_X Timer input select register TISR H'FFF5 TMR_Y Time constant register A_X TCORA_X...
Page 858: Register Bits
Section 28 List of Registers 28.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, so 64-bit registers are shown as 8 lines and 16-bit registers as 2 lines. Register Abbreviation Bit 7 Bit 6...
Page 859 Section 28 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module RSPR8 Bit 71 Bit 70 Bit 69 Bit 68 Bit 67 Bit 66 Bit 65 Bit 64 MCIF RSPR9 Bit 63...
Page 860 Section 28 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module EPSZR1 EP1SZ3 EP1SZ2 EP1SZ1 EP1SZ0 EP2SZ3 EP2SZ2 EP2SZ1 EP2SZ0 EPDR1 FVSR1H — — — — — —...
Page 861 Section 28 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module DTCRA IDE-A IDE-B PMD1 PMD0 BUD2 BUD1 BUD0 DTCRB BOVF_RE BOVF_WE FULLE EMPTYE LOAD MARK REST STCLR DTIDR ID-A3...
Page 862 Section 28 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module CRCCR DORCLR — — — — CRCDIR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0...
Page 863 Section 28 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module BCR2 OWEAC OWENC ABWCP ASTCP ADFULLE EXCKS BUSDIVE CPCSE WSCR2 WMS10 WC11 WC10 WMS21 WMS20 WC22 WC21 WC20 PCSR...
Page 864 Section 28 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module OCRAL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OCRBL Bit 7 Bit 6...
Page 865 Section 28 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCSR_0 WT/IT — RST/NMI CKS2 CKS1 CKS0 WDT_0 TCNT_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
Page 866 Section 28 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module — ICIS BRSTRM BRSTS1 BRSTS0 IOS1 IOS0 WSCR ABW256 AST256 WMS1 WMS0 TCR_0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2...
Page 867 Section 28 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ADDRAH converter ADDRAL — — — — — — ADDRBH ADDRBL — — — — — —...
Page 868 Section 28 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module DADR0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 converter DADR1 Bit 7...
Page 869: 28.3 Register States In Each Operating Mode
Section 28 List of Registers 28.3 Register States in Each Operating Mode High-Speed/ Register Medium- Module Software Hardware Reset Speed Watch Sleep Sub-Active Sub-Sleep Module Abbreviation Stop Standby Standby CMDR0 Initialized — Initialized — Initialized Initialized Initialized Initialized Initialized MCIF CMDR1 Initialized —...
Page 870 Section 28 List of Registers High-Speed/ Register Medium- Module Software Hardware Abbreviation Reset Speed Watch Sleep Sub-Active Sub-Sleep Stop Standby Standby Module RSPR13 Initialized — Initialized — Initialized Initialized Initialized Initialized Initialized MCIF RSPR14 Initialized — Initialized — Initialized Initialized Initialized Initialized Initialized...
Page 871 Section 28 List of Registers High-Speed/ Register Medium- Module Software Hardware Abbreviation Reset Speed Watch Sleep Sub-Active Sub-Sleep Stop Standby Standby Module — * USBIER0 Initialized — — — — — — Initialized — * USBIFR0 Initialized — — — —...
Page 872 Section 28 List of Registers High-Speed/ Register Medium- Module Software Hardware Abbreviation Reset Speed Watch Sleep Sub-Active Sub-Sleep Stop Standby Standby Module ICCRX_1 Initialized — — — — — — — Initialized IIC_1 ICSRA_1 Initialized — — — — — —...
Page 873 Section 28 List of Registers High-Speed/ Register Medium- Module Software Hardware Abbreviation Reset Speed Watch Sleep Sub-Active Sub-Sleep Stop Standby Standby Module ISR16 Initialized — — — — — — — Initialized ISCR16H Initialized — — — — — — —...
Page 874 Section 28 List of Registers High-Speed/ Register Medium- Module Software Hardware Abbreviation Reset Speed Watch Sleep Sub-Active Sub-Sleep Stop Standby Standby Module OCRAH Initialized — — — — — — — Initialized OCRBH Initialized — — — — — — —...
Page 875 Section 28 List of Registers High-Speed/ Register Medium- Module Software Hardware Abbreviation Reset Speed Watch Sleep Sub-Active Sub-Sleep Stop Standby Standby Module PAODR Initialized — — — — — — — Initialized PORT PAPIN Initialized — — — — — —...
Page 876 Section 28 List of Registers High-Speed/ Register Medium- Module Software Hardware Abbreviation Reset Speed Watch Sleep Sub-Active Sub-Sleep Stop Standby Standby Module TCORB_0 Initialized — — — — — — — Initialized TMR_0, TMR_1 TCORB_1 Initialized — — — — —...
Page 877 Section 28 List of Registers High-Speed/ Register Medium- Module Software Hardware Abbreviation Reset Speed Watch Sleep Sub-Active Sub-Sleep Stop Standby Standby Module KMIMR6 Initialized — — — — — — — Initialized KMPCR6 Initialized — — — — — — —...
Page 878 Section 28 List of Registers Rev. 3.00 Jan 25, 2006 page 824 of 872 REJ09B0286-0300...
Page 879: Section 29 Electrical Characteristics
Section 29 Electrical Characteristics Section 29 Electrical Characteristics 29.1 Absolute Maximum Ratings Table 29.1 lists the absolute maximum ratings. Table 29.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage * –0.3 to +4.3 Power supply voltage (VCL pin) –0.3 to +4.3 Input voltage (except ports 6 and 7) –0.3 to V...
Page 880: Dc Characteristics
Section 29 Electrical Characteristics 29.2 DC Characteristics Table 29.2 lists the DC characteristics. Table 29.3 lists the permissible output currents. Table 29.4 lists the I C bus drive characteristics. Table 29.5 lists the USB pin characteristics. Table 29.6 lists the multimedia card interface pin characteristics. Table 29.2 DC Characteristics (1) = 2.7 V to 3.6 V * Conditions: V...
Page 881 Section 29 Electrical Characteristics Test Item Symbol Unit Conditions RES, STBY, MD1, Input low –0.3 — × 0.1 MD0, MD2, FWE voltage NMI, EXTAL, input pins –0.3 — × 0.2 other than (1) and (3) above, and input pins other than applicable pins when IIC, USB, and MCIF are used Output...
Page 882: Table 29.2 Dc Characteristics (2)
Section 29 Electrical Characteristics Table 29.2 DC Characteristics (2) = 2.7 V to 3.6 V * Conditions: V , AV = 2.7 V to 3.6 V, AV = 2.7 V to AV = AV = 0 V Item Symbol Unit Test Conditions I ...
Page 883: Table 29.2 Dc Characteristics (3)
Section 29 Electrical Characteristics Table 29.2 DC Characteristics (3) = 2.7 V to 3.6 V * Conditions: V , AV = 2.7 V to 3.6 V, AV = 2.7 V to AV = AV = 0 V Item Symbol Min Unit Test Conditions Analog power...
Page 884: Table 29.3 Permissible Output Currents
Section 29 Electrical Characteristics Table 29.3 Permissible Output Currents Conditions: V = 2.7 V to 3.6 V, V = 0 V Item Symbol Unit Permissible output low SCL1, SCL0, SDA1, — — current (per pin) SDA0 Ports 1 to 3 —...
Page 885: Table 29.4 I 2 C Bus Drive Characteristics
Section 29 Electrical Characteristics Table 29.4 I C Bus Drive Characteristics Conditions: V = 2.7 V to 3.6V, V = 0 V Applicable Pins: SCL1 and SCL0, SDA1 and SDA0 (bus drive function selected) Item Symbol Unit Test Conditions – Schmitt trigger input ×...
Page 886: Table 29.5 Usb Pin Characteristics
Section 29 Electrical Characteristics Table 29.5 USB Pin Characteristics = 3.3 V ± 0.3 V, DrV = 3.3 V ± 0.3 V, DrV Conditions: V = 0 V Applicable Pins: Driver/receiver input/output (USDP, USDM), USEXCL Item Symbol Unit Test Conditions ...
Page 887: Figure 29.1 Darlington Transistor Drive Circuit (Example)
Section 29 Electrical Characteristics Table 29.6 Multimedia Card Interface Pin Characteristics = 0 V, φ = 5 MHz to 20 MHz Conditions: V = 2.7 V to 3.6 V, V Applicable Pins: MCCLK, MCCSA, MCCSB, MCCMD, MCDAT, MCTxD, MCRxD, MCCMDDIR, MCDATDIR, ExMCCLK, ExMCCSA, ExMCCSB, ExMCCMD, ExMCDAT, ExMCTxD, ExMCRxD, ExMCCMDDIR, ExMCDATDIR Item Symbol...
Page 888: Ac Characteristics
Section 29 Electrical Characteristics 29.3 AC Characteristics Figure 29.3 shows the test conditions for the AC characteristics. C = 30pF : All ports = 2.4 kΩ LSI output pin = 12 kΩ I/O timing test levels • Low level : 0.8 V •...
Page 889: Clock Timing
Section 29 Electrical Characteristics 29.3.1 Clock Timing Table 29.7 shows the clock timing. The clock timing specified here covers clock output (φ), clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation stabilization times. For details of external clock input (EXTAL pin and EXCL pin) timing, see section 26, Clock Pulse Generator.
Page 890: Figure 29.5 Oscillation Stabilization Timing
Section 29 Electrical Characteristics EXTAL DEXT DEXT STBY OSC1 OSC1 φ Figure 29.5 Oscillation Stabilization Timing φ IRQi ( i = 15 to 0) KINi OSC2 ( i = 9 to 0) WUEi ( i = 15 to 8) Figure 29.6 Oscillation Stabilization Timing (Exiting Software Standby Mode) Rev.
Page 891: Control Signal Timing
Section 29 Electrical Characteristics 29.3.2 Control Signal Timing Table 29.8 shows the control signal timing. Only external interrupts NMI, IRQ0 to IRQ15, KIN0 to KIN9, and WUE8 to WUE15 can be operated based on the subclock (φ = 32.768 kHz). Table 29.8 Control Signal Timing = 0 V, φ...
Page 892: Figure 29.7 Reset Input Timing
Section 29 Electrical Characteristics φ RESS RESS RESW Figure 29.7 Reset Input Timing φ NMIS NMIH NMIW IRQi (i = 15 to 0) IRQW IRQS IRQH edge input IRQS level input KINi (i = 9 to 0) WUEi IRQW (i = 15 to 8) IRQS IRQH KIN, WUE...
Page 893: Bus Timing
Section 29 Electrical Characteristics 29.3.3 Bus Timing Table 29.9 shows the bus timing. In subclock (φ = 32.768 kHz) operation, external expansion mode operation cannot be guaranteed. Table 29.9 Bus Timing (1) (Normal Mode and Advanced Mode) = 0 V, φ = 5 MHz to 25 MHz Condition A: V = 3.0 V to 3.6 V, V = 0 V, φ...
Page 894: Figure 29.9 Basic Bus Timing/2-State Access
Section 29 Electrical Characteristics φ A17 to A0, IOS * , CS256, CPCS1 RSD2 RSD1 ACC2 (Read) ACC3 D15 to D0 (Read) WSW1 WRD2 WRD2 HWR, LWR (Write) WSW1 D15 to D0 (Write) Note: * AS is multiplexed with IOS. Either the AS or IOS function can be selected by the IOSE bit of SYSCR. Figure 29.9 Basic Bus Timing/2-State Access Rev.
Page 895: Figure 29.10 Basic Bus Timing/3-State Access
Section 29 Electrical Characteristics φ A17 to A0, IOS * , CS256, CPCS1 AS * RSD1 RSD2 ACC4 (Read) ACC5 D15 to D0 (Read) WRD1 WRD2 HWR, LWR (Write) WSW2 D15 to D0 (Write) Note: * AS is multiplexed with IOS. Either the AS or IOS function can be selected by the IOSE bit of SYSCR. Figure 29.10 Basic Bus Timing/3-State Access Rev.
Page 896: Figure 29.11 Basic Bus Timing/3-State Access With One Wait State
Section 29 Electrical Characteristics φ A17 to A0, IOS * , CS256, CPCS1 AS * (Read) D15 to D0 (Read) HWR, LWR (Write) D15 to D0 (Write) WAIT Note: * AS is multiplexed with IOS. Either the AS or IOS function can be selected by the IOSE bit of SYSCR. Figure 29.11 Basic Bus Timing/3-State Access with One Wait State Rev.
Page 897: Figure 29.12 Cf Interface Basic Timing/3-State Access
Section 29 Electrical Characteristics φ CPA10 to CPA0 (A10 to A0) CPCS1, CPCS2 (P92, P91) RSD2 ACC4 CPOE (P93) RSD1 Read ACC5 CPD15 to CPD0 (P37 to P30) WRD2 WRD1 CPWE (P94) Write WSW2 CPD15 to CPD0 (P37 to P30) Figure 29.12 CF Interface Basic Timing/3-State Access Rev.
Page 898: Figure 29.13 Burst Rom Access Timing/2-State Access
Section 29 Electrical Characteristics T 2 or T 3 φ A17 to A0, IOS * , CS256, CPCS1 AS * RSD2 (Read) ACC3 D15 to D0 (Read) Note: * AS is multiplexed with IOS. Either the AS or IOS function can be selected by the IOSE bit of SYSCR. Figure 29.13 Burst ROM Access Timing/2-State Access Rev.
Page 899: Timing Of On-Chip Peripheral Modules
Section 29 Electrical Characteristics T 2 or T 3 φ A17 to A0, IOS * , CS256, CPCS1 AS * RSD2 (Read) ACC1 D15 to D0 (Read) Note: * AS is multiplexed with IOS. Either the AS or IOS function can be selected by the IOSE bit of SYSCR. Figure 29.14 Burst ROM Access Timing/1-State Access 29.3.4 Timing of On-Chip Peripheral Modules...
Page 900: Table 29.10 Timing Of On-Chip Peripheral Modules (1)
Section 29 Electrical Characteristics Table 29.10 Timing of On-Chip Peripheral Modules (1) = 0 V, φ = 32.768 kHz * , 5 MHz to 25 MHz Condition A: V = 3.0 V to 3.6 V, V = 0 V, φ = 32.768 kHz * , 5 MHz to 20 MHz Condition B: V = 2.7 V to 3.6 V, V Condition A...
Page 901: Figure 29.15 I/O Port Input/Output Timing
Section 29 Electrical Characteristics φ Ports 1 to 9 and A (read) Ports 1 to 6, 8, 9, and A (write) Figure 29.15 I/O Port Input/Output Timing φ FTOD FTOA, FTOB FTIS FTIA, FTIB, FTIC, FTID Figure 29.16 FRT Input/Output Timing φ...
Page 902: Figure 29.18 8-Bit Timer Output Timing
Section 29 Electrical Characteristics φ TMOD TMO0, TMO1 TMOX, TMOY Figure 29.18 8-Bit Timer Output Timing φ TMCS TMCS TMI0, TMI1 TMIX, TMIY TMCWL TMCWH Figure 29.19 8-Bit Timer Clock Input Timing φ TMRS TMI0, TMI1 TMIX, TMIY Figure 29.20 8-Bit Timer Reset Input Timing φ...
Page 903: Figure 29.22 Sck Clock Input Timing
Section 29 Electrical Characteristics SCKW SCKr SCKf SCK2 to SCK0 Scyc Figure 29.22 SCK Clock Input Timing SCK2 to SCK0 TxD2 to TxD0 (transmit data) RxD2 to RxD0 (receive data) Figure 29.23 SCI Input/Output Timing (Clock Synchronous Mode) φ TRGS ADTRG Figure 29.24 A/D Converter External Trigger Input Timing φ...
Page 904: Table 29.11 I C Bus Timing
Section 29 Electrical Characteristics Table 29.11 I C Bus Timing = 0 V, φ = 5 MHz to 25 MHz Condition A: V = 3.0 V to 3.6 V, V = 0 V, φ = 5 MHz to 20 MHz Condition B: V = 2.7 V to 3.6 V, V Item...
Page 905: Figure 29.26 I 2 C Bus Interface Input/Output Timing
Section 29 Electrical Characteristics SDA0 SDA1 SCLH STOS STAH STAS SCL0 SCL1 Sr * SCLL SDAS SDAH Note: * S, P, and Sr indicate the following conditions: S: Start condition P: Stop condition Sr: Retransmission start condition Figure 29.26 I C Bus Interface Input/Output Timing Table 29.12 USB Timing = 3.3 V ±...
Page 906: Figure 29.27 Usb Driver/Receiver Output Timing
Section 29 Electrical Characteristics USDP, USDM Figure 29.27 USB Driver/Receiver Output Timing Table 29.13 Multimedia Card Interface = 0 V, φ = 5 MHz to 20 MHz Conditions: V = 2.7 V to 3.6 V, V • MCIF: ExMCCLK/MCCLK timing CL ≤...
Page 907: Figure 29.28 Multimedia Card Interface Timing
Section 29 Electrical Characteristics ExMCCLK/MCCLK ExMCCSA/MCCSA ExMCCSB/MCCSB ExMCCMD/MCCMD ExMCDAT/MCDAT ExMCTxD/MCTxD ExMCCMDDIR/MCCMDDIR ExMCDATDIR/MCDATDIR ExMCCLK/MCCLK ExMCCMD/MCCMD ExMCDAT/MCDAT ExMCRxD/MCRxD Figure 29.28 Multimedia Card Interface Timing Rev. 3.00 Jan 25, 2006 page 853 of 872 REJ09B0286-0300...
Page 908: Figure 29.29 H-Udi Etck Timing
Section 29 Electrical Characteristics Table 29.14 H-UDI Timing = 0 V, φ = 5 MHz to 25 MHz Condition A: V = 3.0 V to 3.6 V, V = 0 V, φ = 5 MHz to 20 MHz Condition B: V = 2.7 V to 3.6 V, V Item Symbol...
Page 909: Figure 29.30 Reset Hold Timing
Section 29 Electrical Characteristics ETCK RSTHW ETRST TRSTW Figure 29.30 Reset Hold Timing ETCK TMSS TMSH ETMS TDIS TDIH ETDI TDOD ETDO (Six instructions defined in IEEE1149.1) TDOD ETDO (Other instructions) Figure 29.31 H-UDI Input/Output Timing Rev. 3.00 Jan 25, 2006 page 855 of 872 REJ09B0286-0300...
Page 910: A/D Conversion Characteristics
Section 29 Electrical Characteristics 29.4 A/D Conversion Characteristics Tables 29.15 and 29.16 list the A/D conversion characteristics. Table 29.15 A/D Conversion Characteristics (AN7 to AN2 Input: 134/266-State Conversion) Condition A: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, AV = 3.0 V to AV = 0 V, φ...
Page 911: Table 29.16 A/D Conversion Characteristics (Cin7 To Cin0 Input: 134/266-State Conversion)
Section 29 Electrical Characteristics Table 29.16 A/D Conversion Characteristics (CIN7 to CIN0 Input: 134/266-State Conversion) Condition A: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, AV = 3.0 V to AV = 0 V, φ = 5 MHz to 25 MHz = AV Condition B: V = 2.7 V to 3.6 V, AV...
Page 912: D/A Conversion Characteristics
Section 29 Electrical Characteristics 29.5 D/A Conversion Characteristics Table 29.17 lists the D/A conversion characteristics. Table 29.17 D/A Conversion Characteristics Condition A: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, AV = 3.0 V to AV = 0 V, φ...
Page 913: Flash Memory Characteristics
Section 29 Electrical Characteristics 29.6 Flash Memory Characteristics Table 29.18 lists the flash memory characteristics. Table 29.18 Flash Memory Characteristics Condition: V = 3.0 V to 3.6 V, V = 0 V Test Item Symbol Unit Conditions Programming time * —...
Page 914 Section 29 Electrical Characteristics 2. Programming time per 128 bytes (Shows the total period for which the P bit in FLMCR1 is set. It does not include the program verification time.) 3 Block erase time (Shows the total period for which the E bit in FLMCR1 is set. It does not include the erase verification time.) 4.
Page 915: Appendix
Appendix Appendix I/O Port States in Each Pin State Hardware Software Program Port Name Operating Standby Standby Watch Sleep Subsleep Subactive Execution Pin Name Mode Reset Mode Mode Mode Mode Mode Mode State kept * kept * kept * kept * Port 1 2, 3 (EXPE = 1) Address...
Page 916 Appendix Hardware Software Program Port Name Operating Standby Standby Watch Sleep Subsleep Subactive Execution Pin Name Mode Reset Mode Mode Mode Mode Mode Mode State Port 7 2, 3 (EXPE = 1) Input port Input port 2, 3 (EXPE = 0) Port 8 2, 3 (EXPE = 1) kept...
Page 917: B. Product Lineup
Appendix Product Lineup Product Type Type Code Mark Code Package (Code) H8S/2158 F-ZTAT version HD64F2158 F2158VBQ25 112-pin TFBGA (TBP-112A) Rev. 3.00 Jan 25, 2006 page 863 of 872 REJ09B0286-0300...
Page 918 Appendix Package Dimensions For package dimensions, dimensions described in Renesas Package Data Book have priority. JEITA Package Code RENESAS Code Previous Code MASS[Typ.] T-TFBGA112-10x10-0.80 TTBG0112GA-A TBP-112A/TBP-112AV 0.2g × Dimension in Millimeters Reference Symbol 10.00 10.00 0.20 0.30 1.20 0.35 0.40 0.45...
Page 919 Index Index 14-Bit PWM Timer (PWMX)....273 Block Transfer Mode ......159 16-Bit Access Space ....... 123 Boot Mode ..........728 16-Bit Count Mode ......... 335 Boundary overflow........202 16-Bit Free-Running Timer (FRT) ..287 Boundary Scan ........756 16-Bit, 2-State Access Space ....127 Branch Instructions ........41 16-Bit, 3-State Access Space ....
Page 920 Index CPU Operating Modes......20 HSYNCO Output ........370 CRC Operation Circuit ......467 Crystal Oscillator ........762 I/O Ports..........205 I/O Select Signals........122 D/A Converter ........691 C Bus Formats ........516 data direction register ......205 C bus interface........539 data register..........
Page 921 Index TEI ..........459, 460 Number of DTC Execution States...163 TXI........459, 460. See Number of FIFO Bytes......174 USBI0 ..........625 USBI1 ..........625 On-Board Programming......727 USBI2 ..........625 Operating Modes........55 USBI3 ..........625 Operation field ..........43 WOVI ..........382 Operation Reservation Commands..513 WUE15 to WUE8 Interrupts....
Page 922 Index ADCSR....... 701, 802, 813, 822 DTCERE ..... 150, 797, 808, 818 ADDR......700, 801, 813, 822 DTCRA ....... 173, 795, 807, 817 BAR ............ 170 DTCRB ....... 175, 795, 807, 817 BARA ......78, 797, 808, 818 DTCRC ..........180 BARB ......
Page 923 Index FVSR1L...... 562, 794, 806, 816 KMIMRA...... 83, 802, 813, 823 FVSR2H ..... 562, 793, 805, 816 KMPCR6..... 234, 802, 813, 823 FVSR2L...... 562, 793, 805, 816 LPWRCR ....774, 797, 809, 819 FVSR3H ..... 562, 793, 805, 816 MDCR......56, 800, 811, 821 FVSR3L......
Page 924 Index PCSR ....269, 279, 797, 809, 819 TCONRI...... 348, 803, 814, 823 PTCNT0 ..... 260, 797, 808, 819 TCONRO ....352, 803, 814, 823 PTTER0 ...... 564, 794, 806, 816 TCONRS..... 354, 803, 814, 823 PWDPRA....266, 801, 812, 822 TCORA .......
Page 925 Index WSCR ......110, 800, 812, 821 stack pointer (SP) ........26 WSCR2 ....... 112, 797, 809, 819 Stack Status ..........70 WUEMR3 ..... 83, 802, 813, 823 Start condition .........517 Relative Address Commands....657 Stop condition .........517 Repeat Mode........... 158 Subactive Mode........787 Reset ............
Page 926 Index Rev. 3.00 Jan 25, 2006 page 872 of 872 REJ09B0286-0300...
Page 927 Publication Date: 1st Edition, September 2001 Rev.3.00, January 25, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. ©2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Page 928 Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Page 929 16 H8S/2158 Group, H8S/2158 F-ZTAT Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0286-0300...

Renesas H8S/2158 User Manual

Section 1 Overview

Section 2 CPU

Section 3 MCU Operating Modes

Section 4 Exception Handling

Section 5 Interrupt Controller

Section 6 Bus Controller

Section 7 Data Transfer Controller (DTC)

Section 8 RAM-FIFO Unit (RFU)

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