Description Of Operation - Renesas Hitachi H8S/2194 Series Hardware Manual

Bit 4: Error Data Latch Signal Selection Bit (N/V)
Selects the latch signal of error data.
Bit 4
N/V Description
0 HSW (VideoFF) signal
1 NHSW (NarrowFF) signal
Bit 3: Edge Selection Bit (HSWES)
Selects the edge of the error data latch signal (HSW or NHSW).
Bit 3
HSWES Description
0 Latches at the rising edge
1 Latches at the falling edge
Bits 2 to 0: Reserved
No read or write is valid.
28.7.5

Description of Operation

The drum phase error detector detects the phase error based on the reference value set in the
drum phase preset data register 1 and 2 (DPPR1, DPPR2). The reference values set in DPPR1
and DPPR2 are preset in the counter by the REF30P signal, and counted up by the clock
selected. The latch of the error data can be selected between the rising or falling edge of HSW
(NHSW). The error data detected in the error data automatic transmission mode (DFEPS bit of
DFUCR = 0) is sent to the digital filter circuit automatically. In software transmission mode
(DFEPS bit of DFUCR = 1), the data written in DPER1 and DPER2 is sent to the digital filter
circuit. The error data is signed binary. It takes a positive number (+) if the phase is behind the
specified phase, a negative number (-) if in advance of the specified phase, or 0 if it had no
phase error (revolving at the specified phase). Figures 28.30 and 28.31 show examples of
operation to detect a drum phase error.
(a) Drum phase error detection counter
The drum phase error detection counter stops the counter when overflow or latch occurred.
At the same time, it generates an interrupt request (IRRDRM3), setting the overflow flag
(DPOVF) if overflow occurred. Clear DPOVF by writing 0 after reading 1. If setting the
flag and writing 0 take place simultaneously, the latter is nullified.
(b) Interrupt request
IRRDRM3 is generated by the HSW (NHSW) signal latch and the overflow of the error
detection counter.
Rev. 2.0, 11/00, page 698 of 1037
(Initial value)
(Initial value)