Sleep Mode; Clearing Sleep Mode - Renesas Hitachi H8S/2194 Series Hardware Manual

4.4

Sleep Mode

4.4.1 Sleep Mode
If a SLEEP instruction is executed when the SSBY bit in SBYCR and the LSON bit in
LPWRCR are both cleared to 0, the CPU enters sleep mode. In sleep mode, CPU operation
stops but the contents of the CPU's internal registers are retained. Other supporting modules
(excluding the servo circuit and 12-bit PWM) do not stop.
4.4.2

Clearing Sleep Mode

Sleep mode is cleared by any interrupt, or with the 5(6 pin.
(1) Clearing with an Interrupt
When an interrupt request signal is input, sleep mode is cleared and interrupt exception
handling is started. Sleep mode will not be cleared if interrupts are disabled, or if interrupts
other than NMI have been masked by the CPU.
(2) Clearing with the 5(6 Pin
When the 5(6 pin is driven low, the reset state is entered. When the 5(6 pin is driven high
after the prescribed reset input period, the CPU begins reset exception handling.
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