Renesas Hitachi H8S/2194 Series Hardware Manual page 582

SCL
(Master output) 7
SCL
(Slave output)
SDA
Bit 1
(Master output)
Data 1
SDA
(Slave output)
RDRF
IRIC
ICDRS
ICDRR
User processing
Figure 25.10 Example of Timing in Slave Receive Mode (MLS = ACKB = 0) (2)
8 9 1
Bit 0 Bit 7
[4]
A
Interrupt
request
generated
Data 1
Data 1
[5] Read ICDR [5] Clear IRIC
2 3 4 5
Bit 6 Bit 5 Bit 4 Bit 3
Data 2
Rev. 2.0, 11/00, page 555 of 1037
6 7 8 9
Bit 2 Bit 1 Bit 0
[4]
A
Interrupt
request
generated
Data 2
Data 2