Renesas Hitachi H8S/2194 Series Hardware Manual page 596

16-bit single-chip microcomputer
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2
Table 25.7 I
C Bus Timing (with Maximum Influence of t
t
cyc
Item
Indication
t
0.5t
SCLHO
SCLO
(-t
)
Sr
t
0.5t
SCLLO
SCLO
(-t
)
Sf
t
0.5t
-1t
BUFO
SCLO
cyc
(-t
)
Sr
t
0.5t
-1t
STAHO
SCLO
cyc
(-t
)
Sf
t
1t
STASO
SCLO
(-t
)
Sr
t
0.5t
+2t
STOSO
SCLO
(-t
)
Sr
3
t
1t
*
-3t
SDASO
SCLLO
(master)
(-t
)
Sr
3
t
1t
*
-12t
SDASO
SCLL
cyc
(slave)
(-t
)
Sr
t
3t
SDAHO
cyc
Notes: 1. Does not meet the I
following is necessary: (a) secure a start/stop condition issuance interval; (b) adjust
the rise and fall times by means of a pull-up resistor and capacitive load; (c) reduce
the transfer rate; (d) select slave devices whose input timing permits this output
timing.
The values in the above table will vary depending on the settings of the IICX bit and
bits CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the
maximum transfer rate; therefore, whether or not the I
are met must be determined in accordance with the actual setting conditions.
2. Value when the IICX bit is set to 1. When the IICX bit is cleared to 0, the value is (t
- 6t
).
cyc
3. Calculated using the I
speed mode: 1300 ns min.).
Time Indication (at Maximum Transfer Rate) [ns]
t
/t
Sr
Sf
Influence
(Max.)
Normal mode −1000
−300
High-speed
mode
Normal mode −250
−250
High-speed
mode
Normal mode −1000
−300
High-speed
mode
Normal mode −250
−250
High-speed
mode
Normal mode −1000
−300
High-speed
mode
Normal mode −1000
cyc
−300
High-speed
mode
Normal mode −1000
cyc
−300
High-speed
mode
Normal mode −1000
2
*
−300
High-speed
mode
Normal mode 0
High-speed
0
mode
2
C bus interface specification. Remedial action such as the
2
C bus specification values (standard mode: 4700 ns min.; high-
/t
)
Sr
Sf
2
I
C Bus
Specification
φ = 5 MHz
(Min.)
4000
4000
600
950
4700
4750
*1
1300
1000
*1
4700
3800
*1
1300
750
4000
4550
600
800
4700
9000
600
2200
4000
4400
600
1350
250
3100
100
400
250
1300
−1400
*1
100
0
600
0
2
C bus interface specifications
Rev. 2.0, 11/00, page 569 of 1037
φ = 8 MHz
φ = 10 MHz
*1
*1
3875
3900
*1
*1
825
850
4625
4650
875
900
9000
9000
2200
2200
4250
4200
1200
1150
3325
3400
625
700
2200
2500
−500
−200
*1
*1
375
300
SCLL

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