Renesas Hitachi H8S/2194 Series Hardware Manual page 921

Instruction Mnemonic
SHAL SHAL.B Rd
SHAL.B #2,Rd
SHAL.W Rd
SHAL.W #2,Rd
SHAL.L ERd
SHAL.L #2,ERd
SHAR SHAR.B Rd
SHAR.B #2,Rd
SHAR.W Rd
SHAR.W #2,Rd
SHAR.L ERd
SHAR.L #2,ERd
SHLL SHLL.B Rd
SHLL.B #2,Rd
SHLL.W Rd
SHLL.W #2,Rd
SHLL.L ERd
SHLL.L #2,ERd
SHLR SHLR.B Rd
SHLR.B #2,Rd
SHLR.W Rd
SHLR.W #2,Rd
SHLR.L ERd
SHLR.L #2,ERd
SLEEP SLEEP
STC STC.B CCR.Rd
STC.B EXR,Rd
STC.W CCR,@ERd
STC.W EXR,@ERd
STC.W CCR,@(d:16,ERd)
STC.W EXR,@(d:16,ERd)
STC.W CCR,@(d:32,ERd)
STC.W EXR,@(d:32,ERd)
STC.W CCR,@-ERd
STC.W EXR,@-ERd
STC.W CCR,@aa:16
STC.W EXR,@aa:16
STC.W CCR,@aa:32
STC.W EXR,@aa:32
STM STM.L (ERn-ERn+1),
@-Sp
STM.L (ERn-ERn+2),
@-Sp
STM.L (ERn-ERn+3),
@-Sp
STMAC STMAC MACH,ERd
STMAC MACL,ERd
SUB SUB.B Rs,Rd
SUB.W #xx:16,Rd
SUB.W Rs,Rd
SUB.L #xx:32,ERd
SUB.L ERs,ERd
SUBS SUBS #1/2/4,ERd
Rev. 2.0, 11/00, page 894 of 1037
Branch
Instruction Address
Fetch Read
I J
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
3
3
5
5
2
2
3
3
4
4
2
2
2
Cannot be used in this LSI.
1
2
1
3
1
1
Stack Byte Data
Operation Access
K L
4
6
8
Word Data Internal
Access Operation
M N
1
1
1
1
1
1
1
1 1
1 1
1
1
1
1
1
1
1