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(7) FIFO Timing Pattern Register 2 (FTPRB)
15
Bit :
FTPRB15 FTPRB14 FTPRB13 FTPRB12 FTPRB11 FTPRB10 FTPRB9 FTPRB8 FTPRB7 FTPRB6 FTPRB5 FTPRB4 FTPRB3 FTPRB2 FTPRB1 FTPRB0
Initial value :
*
R/W :
W
Note: * Undetermined
FTPRB is a register to write the timing pattern data of FIFO2. The timing data written in
FTPRB is written at the same time to the position pointed by the buffer pointer of FIFO2
together with the buffer data of FPDRB.
FTPRB is a 16-bit write-only register. Only a word access is valid. If a byte access is
attempted, resulting operation is not assured. It is not initialized by a reset, stand-by or module
stop, accordingly be sure to write data before use.
(8) DFG Reference Register 1 (DFCRA)
7
Bit :
ISEL2
Initial value :
0
R/W :
W
Note: * Undetermined
DFCRA is a register which determines the operation of the HSW timing generator as well as the
starting point of the timing of FIFO1.
DFCRA is an 8-bit write-only register. It is not initialized by a reset, stand-by or module stop,
accordingly be sure to write data before use.
Note: Its address is shared with the DFG reference counter register (DFCTR). Accordingly,
the value of DFCTR is read out in the low-order five bits if a read is attempted.
Bit 7: Interrupt Selection Bit (ISEL2)
Selects the factor which causes an interrupt. (IRRHSW2)
Bit 7
ISEL2
Description
0
Generates an interrupt request by the clear signal of the 16-bit timer counter
1
Generates an interrupt request by the VD signal in PB mode
Rev. 2.0, 11/00, page 666 of 1037
14
13
12
11
10
*
*
*
*
*
W
W
W
W
W
6
5
CCLR
CKSL
0
0
W
W
9
8
7
6
5
*
*
*
*
*
W
W
W
W
W
4
3
DFCRA4 DFCRA3 DFCRA2 DFCRA1
*
*
W
W
4
3
2
1
0
*
*
*
*
*
W
W
W
W
W
2
1
0
DFCRA0
*
*
*
W
W
W
(Initial value)
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