Renesas Hitachi H8S/2194 Series Hardware Manual page 579

SCL
8
(master output)
SDA
Bit0
(slave output)
Data 2
[8]
SDA
(master output)
IRIC
IRTR
ICDR
Data 1
User processing [9] IRIC clearance
Figure 25.8 Example of Master Receive Mode Operation Timing
Rev. 2.0, 11/00, page 552 of 1037
9 1 2 3 4
Bit7 Bit6 Bit5 Bit4
Data 3
[5]
A
Data 2
[6] ICDR read [7] IRIC clearance
(Data 2)
These processes are executed continuously.
(MLS = ACKB = 0, WAIT = 1) continued
5 6 7 8
Bit3 Bit2 Bit1 Bit0
[8]
[9] IRIC Clearance
9 1 2
Bit7 Bit6
Data 4
[5]
A
Data 3
[6] ICDR read [7] IRIC clearance
(Data 3)
These processes are executed continuously.