Serial Status Register (Ssr1) - Renesas Hitachi H8S/2194 Series Hardware Manual

Bit 1 Bit 0
CKE1 CKE0
0 0
1
1 0
1
Notes: 1. Initial value
2. Outputs a clock of the same frequency as the bit rate.
3. Inputs a clock with a frequency 16 times the bit rate.
23.2.7

Serial Status Register (SSR1)

Bit : 7
TDRE
Initial value : 1
R/(W) *
R/W :
Note: * Only 0 can be written to clear the flag.
SSR1 is an 8-bit register containing status flags that indicate the operating status of the SCI1,
and multiprocessor bits.
SSR1 can be read or written to by the CPU at all times. However, 1 cannot be written to flags
TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be
read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified.
SSR1 is initialized to H'84 by a reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.
Description
Asynchronous mode
Clock synchronous
mode
Asynchronous mode
Clock synchronous
mode
Asynchronous mode
Clock synchronous
mode
Asynchronous mode
Clock synchronous
mode
6 5
RDRF ORER
0 0
R/(W) * R/(W) * R/(W) *
Internal clock/SCK1 pin functions as I/O
*1
port
Internal clock/SCK1 pin functions as serial
*1
clock output
Internal clock/SCK1 pin functions as clock
*2
output
Internal clock/SCK1 pin functions as serial
clock output
External clock/SCK1 pin functions as clock
*3
input
External clock/SCK1 pin functions as serial
clock input
External clock/SCK1 pin functions as clock
*3
input
External clock/SCK1 pin functions as serial
clock input
4 3
FER PER TEND
0 0
R/(W) *
Rev. 2.0, 11/00, page 453 of 1037
2 1 0
MPB MPBT
1 0 0
R R R/W