Trap Address Register 2 To 0 (Tar2 To Tar0) - Renesas Hitachi H8S/2194 Series Hardware Manual

Bit 1: Trap Control 1 (TRC1)
Sets ON/OFF operation of the address trap function 1.
Bit 1
TRC1 Description
0 Address trap function 1 disabled
1 Address trap function 1 enabled
Bit 0: Trap Control 0 (TRC0)
Sets ON/OFF operation of the address trap function 0.
Bit 0
TRC0 Description
0 Address trap function 0 disabled
1 Address trap function 0 enabled
27.2.2

Trap Address Register 2 to 0 (TAR2 to TAR0)

Bit :
A23
Initial value :
R/W
R/W :
Bit :
A15
Initial value :
R/W : R/W
Bit :
Initial value :
R/W : R/W
The TAR is composed of three 8-bit readable/writable registers (TARnA, B, and C)(n = 2 to 0)
The TAR sets the address to trap. The function of the TAR2 to TAR0 is the same.
The TAR is initialized to H'00 by a reset.
7 6 5
A22 A21
0 0 0
R/W R/W
7 6 5
A14 A13
0 0 0
R/W R/W
7 6 5
A7 A6 A5
0 0 0
R/W R/W
4 3 2
A20 A19 A18
0
0 0
R/W R/W R/W
4 3 2
A12 A11 A10
0 0 0
R/W R/W R/W
4 3 2
A4 A3 A2
0 0 0
R/W R/W R/W
Rev. 2.0, 11/00, page 593 of 1037
(Initial value)
(Initial value)
1 0
A17 A16
0 0
R/W R/W
1 0
A9 A8
0 0
R/W R/W
1 0
—
A1
0 0
—
R/W