Descriptions Of Respective Registers; Timer L Mode Register (Lmr) - Renesas Hitachi H8S/2194 Series Hardware Manual

15.2

Descriptions of Respective Registers

15.2.1

Timer L Mode Register (LMR)

Bit :
LMIF
Initial value :
R /(W) *
R/W :
Note: * Only 0 can be written to clear the flag.
The timer L mode register (LMR) is an 8-bit read/write register which works to control the
interrupts, to select between up-counting and down-counting and to select the clock source.
When reset, the LMR is initialized to H'30.
Bit 7: Timer L Interrupt Requesting Flag (LMIF)
This is the Timer L interrupt requesting flag. It indicates occurrence of overflow or underflow
of the LTC or occurrence of compare match clear.
Bit 7
LMIF Description
0 [Clearing conditions]
When 0 is written after reading 1
1 [Setting conditions]
When the LTC overflows, underflows or when compare match clear has occurred
Bit 6: Enabling Interrupt of the Timer L (LMIE)
This bit works to permit/prohibit occurrence of interrupt of the Timer L when the LTC
overflows, underflows or when compare match clear has occurred.
Bit 6
LMIE Description
0 Prohibits occurrence of interrupt of the Timer L
1 Permits occurrence of interrupt of the Timer L
Bits 5 and 4: Reserved
When they are read, 1 will always be readout. Writes are disabled.
Bit 3: Up-count/Down-count Control (LMR3)
This bit is for selection if the Timer L is to be controlled to the up-counting function or down-
counting function.
Rev. 2.0, 11/00, page 324 of 1037
7 6 5
LMIE
—
0 0 1
—
R/W
4 3 2
IMR3 IMR2
—
1 0 0
—
R/W R/W
1 0
IMR1 IMR0
0 0
R/W R/W
(Initial value)
(Initial value)