Prescalar W (Psw); Stable Oscillation Wait Time Count - Renesas Hitachi H8S/2194 Series Hardware Manual

22.4.2

Prescalar W (PSW)

PSW is a counter that uses the subclock as an input clock. The PSW also generates the input
clock of the timer A. In this case, the timer A functions as a clock time base.
When reset, the PSW is initialized to H'00, and starts increment after reset has been released.
Even if the mode has been shifted to the standby mode *, watch mode *, subactive mode *, and
subsleep mode *, the PSW continues the operation as long as the clocks are supplied by the X1
and X2 pins.
The PSW can also be initialized to H'00 by setting the TMA3 and TMA2 bits of the timer mode
register A (TMA) to 11.
Note: * When the timer A is in module stop mode, the operation is stopped.
Figure 22.2 shows the supply of the clocks to the peripheral function by the PSS and PSW.
OSC1
System
clock
oscillator
OSC2
X1
Subclock
oscillator
X2
22.4.3

Stable Oscillation Wait Time Count

For the count of the stable oscillation stable wait time during the return from the low power
consumption mode excluding the sleep mode, see section 4, Power-Down State.
System
clock
fosc
duty
correction
circuit
Subclock
(fx)
frequency
dividers
w
(1/2, 1/4, and 1/8)
Figure 22.2 Clock Supply
Prescalar S
Medium
speed clock
frequency divider
w/4
Prescalar W
System clock
selection
Rev. 2.0, 11/00, page 439 of 1037
/131072 to /2
Timer
SCI
TMOW pin
w/128
Timer A
CPU
ROM
RAM
Peripheral register
I/O port