Renesas Hitachi H8S/2194 Series Hardware Manual page 595

2
(5) The I C bus interface specification for the SCL rise time tsr is under 1000 ns (300 ns for
high-speed mode). In master mode, the I
synchronizes one bit at a time during communication. If t
to V ) exceeds the time determined by the input clock of the I
IH
period of SCL is extended. The SCL rise time is determined by the pull-up resistance and
load capacitance of the SCL line. To insure proper operation at the set transfer rate, adjust
the pull-up resistance and load capacitance so that the SCL rise time does not exceed the
values given in table 25.6.
Table 25.6 Permissible SCL Rise Time (t
t
cyc
IICX Indication
0 7.5t
cyc
1 17.5t
cyc
2
(6) The I C bus interface specifications for the SCL and SDA rise and fall times are under 1000
ns and 300 ns. The I
t , as shown in table 25.5. However, because of the rise and fall times, the I
cyc
specifications may not be satisfied at the maximum transfer rate. Table 25.7 shows output
timing calculations for different operating frequencies, including the worst-case influence of
rise and fall times.
t fails to meet the I
BUFO
(a) to provide coding to secure the necessary interval (approximately 1 µs) between issuance
of a stop condition and issuance of a start condition, or (b) to select devices whose input
timing permits this output timing for use as slave devices connected to the I
t in high-speed mode and t
SCLLO
specifications for worst-case calculations of t
investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and
capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting
devices whose input timing permits this output timing for use as slave devices connected to
2
the I C bus.
Rev. 2.0, 11/00, page 568 of 1037
2
sr
Time Indication [ns]
2
I C Bus
Specification
(Max.)
Normal 1000
mode
High-speed 300
mode
Normal 1000
mode
High-speed 300
mode
2
C bus interface SCL and SDA output timing is prescribed by t
2
C bus interface specifications at any frequency. The solution is either
in standard mode fail to satisfy the I
STASO
C bus interface monitors the SCL line and
(the time for SCL to go from low
sr
2
) Values
φ = 5 MHz
←
←
←
←
/t . Possible solutions that should be
Sr Sf
C bus interface, the high
φ = 8 MHz φ = 10 MHz
937 750
← ←
← ←
← ←
2
C bus interface
2
C bus.
2
C bus interface
and
Scyc