Renesas Hitachi H8S/2194 Series Hardware Manual page 657

Bit 5: Manual Selection Bit (CVS)
Selects whether the REF30 signals are generated in sync with VD or operated free-run in manual
mode (VNA = 0). (No selection is reflected in PB mode, except in TBC mode.)
Bit 5
CVS Description
0 Sync with VD
1 Free-run operation
Bit 4: External Signals Sync Selection Bit (REX)
Selects whether the REF30 signals are generated in sync with VD or in free-run or in sync with
the external signals. (Valid in both PB and REC modes.)
Bit 4
REX Description
0 VD signals or free-run
1 Sync with external signals
Bit 3: DVCFG2 Sync Selection Bit (CRD)
Selects whether the reset timing in the CREF signals generation is immediately after switching
from PB (ASM) mode to REC mode or is in sync with the DVCFG2 signals immediately after
the switching.
Bit 3
CRD Description
0 On switching modes
1 In sync with DVCFG2 signals
Bit 2: ODD/EVEN Edge Switching Selection Bit (OD/EV)
Selects whether REF30P signals are generated by ODD of the field signals or EVEN when in
REC mode.
Bit 2
OD/EV Description
0 Generated at the rising edge (EVEN) of the field signals
1 Generated at the falling edge (ODD) of the field signals
Rev. 2.0, 11/00, page 630 of 1037
(Initial value)
(Initial value)
(Initial value)
(Initial value)