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12.3
Operation
The Timer A is an 8-bit timer for use as an interval timer and as a clock time base connecting to
a 32.768 kHz crystal oscillator.
12.3.1
Operation as the Interval Timer
When the TMA3 bit of the TMA is cleared to 0, the Timer A works as an 8-bit interval timer.
When resetince the TCA is cleared to H'00 and as the TMA3 bit is cleared to 0, the Timer A
continues counting up as the interval counter without interrupts right after resetting.
As the operation clock for the Timer A, selection can be made from eight different types of
internal clocks being output from the PSS by the TMA2 to TMA0 bits of the TMA.
When the clock signal is input after the reading of the TCA reaches H'FF, the Timer A
overflows and the TMAOV bit of the TMA will be set to 1. At this time, when the TMAIE bit
of the TMA is 1, interrupt occurs.
When overflowing occurs, the reading of the TCA returns to H'00 before resuming counting up.
Consequently, it works as the interval timer to produce overflow outputs periodically at every
256 input clocks.
12.3.2
Operation of the Timer for Clocks
When the TMA3 bit of the TMA is set to 1, the Timer A works as a time base for the clock.
As the overflow cycles for the Timer A, selection can be made from four different types by
counting the clock being output from the PSW by the TMA1 bit and TMA0 bit of the TMA.
12.3.3
Initializing the Counts
When the TMA3 and TMA2 bits are set to 11, the PSW and TCA will be cleared to H'00 to
come to a stop.
At this state, writing 10 to the TMA3 bit and TMA2 bit makes the Timer A to start counting
from H'00 under the time base mode for clocks.
After clearing the PSW and TCA using the TMA3 and TMA2 bits, writing 00 or 01 to the
TMA3 bit and TMA2 bit work to make the Timer A to start counting from H'00 under the
interval timer mode. However, since the PSS is not cleared, the period to the first count is not
constant.
Rev. 2.0, 11/00, page 294 of 1037
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