Renesas Hitachi H8S/2194 Series Hardware Manual page 734

Bit 5: Counter Overflow Flag (CFOVF)
The CFOVF flag indicates overflow of the 16-bit counter. It is cleared by writing 0. Write 0
after reading 1. Also, setting has the highest priority in this flag. If a flag set and 0 write occurs
simultaneously, the latter is nullified.
Bit 5
CFOVF Description
0 Normal state
1 Indicates that an overflow has occurred in the counter
Bit 4: Error Data Limit Function Selection Bit (CFRFON)
Makes the error data limit function valid. (Limit values are the values set in the lock range data
register (CFRUDR, CFRLDR)).
Bit 4
CFRFON Description
0 Limit function off
1 Limit function on
Bit 3: Capstan Lock Flag (CF-R/UNR)
Sets a flag if an underflow occurred in the capstan lock counter.
Bit 3
CF-R/UNR Description
0 Indicates that the capstan speed system is not locked
1 Indicates that the capstan speed system is locked
Bit 2: Capstan Phase System Filter Computation Automatic Start Bit (CPCNT)
Sets on the filter computation of the phase system if an underflow occurred in the capstan lock
counter.
Bit 2
CPCNT Description
0 Does not perform the filter computation by detection of the capstan lock
1 Set on the filter computation of the phase system when capstan lock is detected
(Initial value)
(Initial value)
(Initial value)
(Initial value)
Rev. 2.0, 11/00, page 707 of 1037