Renesas Hitachi H8S/2194 Series Hardware Manual page 972

H'D098: DVCTL Control Register CTVC: Frequency Divider
Bit :
7
CEX
Initial value :
0
W
R/W :
External sync signal edge select bit
0 Rising edge
1 Falling edge
DVCTL signal generation select bit
0 Generated by PB-CTL signal
1 Generated by external input signal
Note: * Undetermined
H'D099: CTL Frequency Division Register CTLR: Frequency Divider
Bit :
7
CTL7
Initial value :
0
R/W : W
6 5 4
CEG — —
0 1 1
— —
W
6 5
CTL6 CTL5
0 0
W W
3 2
— CFG
1 *
—
R
HSW flag
0 HSW level is low
1 HSW level is high
CFG flag
0 CFG level is low
1 CFG level is high
4 3
CTL4 CTL3 CTL2
0 0
W W
Rev. 2.0, 11/00, page 945 of 1037
1 0
HSW CTL
* *
R R
CTL flag
0 REC or PB-CTL level is low
1 REC or PB-CTL level is high
2 1 0
CTL1 CTL0
0 0 0
W W W