Acceleration And Braking Processes Of The Capstan Motor - Renesas Hitachi H8S/2194 Series Hardware Manual

16-bit single-chip microcomputer
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(2) Setting the timer R load register 3 (TMRL3)
Set the slow tracking delay value. When the delay count is "n", the set value should be
(n - 1).
Regarding the delaying duration, see figure 16.2 Exemplary time series movements
when a slow reproduction is being performed.
16.5.4

Acceleration and Braking Processes of the Capstan Motor

When making intermittent movements such as those for slow reproductions or for still
reproductions, it is necessary to conduct quick accelerations and abrupt stoppings of the capstan
motor. The acceleration and braking processes will function to check if the revolution of a
capstan motor has reached the prescribed rate when accelerated or braked. For this purpose, the
TMRU-2 (reloading function) should be used.
The acceleration and braking processes should be employed when making special reproductions,
in combination with the slow tracking mono-multi function.
• Exemplary settings for the acceleration process
(1) Setting the timer R mode register 1 (TMRM1)
AC/BR bit (Bit 6) = 1: Acceleration process
RLD bit (Bit 5) = 1: The TMRU-2 is to be used as the reload timer.
RLCK bit (Bit 4) = 0: The TMRU-2 is to reload at the rising edge of the CFG.
PS21 and PS20 (Bits 3 and 2) = Other than (0, 0): The dividing clock is to be used as the
clock source for the TMRU-2.
(2) Setting the timer R load register 2 (TMRL2)
Set the count reading for the duration until the acceleration process finishes. When the
count is "n", the set value should be (n - 1).
Regarding the duration until the acceleration process finishes, see figure 16.2 Exemplary
time series movements when a slow reproduction is being performed.
• Exemplary settings for the braking process
(1) Setting the timer R mode register 1 (TMRM1)
AC/BR bit (Bit 6) = 0: Braking process
RLD bit (Bit 5) = 1: The TMRU-2 is to be used as the reload timer.
RLCK bit (Bit 4) = 0: The TMRU-2 is to reload at the rising edge of the CFG.
PS21 and PS20 (Bits 3 and 2) = Other than (0, 0): The dividing clock is to be used as the
clock source for the TMRU-2.
Rev. 2.0, 11/00, page 353 of 1037

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