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(3) Data Transfer Operations
(a) SCI1 Initialization (Asynchronous Mode)
Before transmitting and receiving data, first clear the TE and RE bits in SCR1 to 0, then
initialize the SCI1 as described below.
When the operating mode, transfer format, etc., is changed, the TE and RE bits must be
cleared to 0 before making the change using the following procedure. When the TE bit is
cleared to 0, the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE
bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the
contents of RDR1.
When an external clock is used the clock should not be stopped during operation,
including initialization, since operation is uncertain.
Figure 23.4 shows a sample SCI1 initialization flowchart.
Start initialization
Clear TE and RE bits in SCR1 to 0
Set CKE1 and CKE0 bits in SCR1
(TE, RE bits 0)
Set data transfer format
in SMR1 and SCMR1
Set value in BRR1
1-bit interval elapsed?
Set TE and RE bits in SCR1 to 1,
and set RIE, TIE, TEIE,
and MPIE bits
<Initialization completed>
Wait
No
Yes
Figure 23.4 Sample SCI Initialization Flowchart
Set the clock selection in SCR1.
[1]
Be sure to clear bits RIE, TIE, TEIE, and
MPIE, and bits TE and RE, to 0.
When the clock is selected in
asynchronous mode, it is output
immediately after SCR1 settings are made.
[1]
[2]
Set the data transfer format in SMR1 and
SCMR1.
Write a value corresponding to the bit rate
[3]
to BRR1. This is not necessary if an
[2]
external clock is used.
Wait at least one bit interval, then set the
[4]
[3]
TE bit or RE bit in SCR1 to 1. Also set the
RIE, TIE, TEIE, and MPIE bits.
Setting the TE and RE bits enables the
SO1 and SI1 pins to be used.
[4]
Rev. 2.0, 11/00, page 471 of 1037
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