Renesas Hitachi H8S/2194 Series Hardware Manual page 717

(d) Interrupt request
IRRDRM1 is generated by the NCDFG signal latch and the overflow of the error detection
counter. IRRDRM2 is generated by detection of lock (after the detection of the number of
times of setting).
NCDFG signal
Error data latch
signal (DFG )
Preset data
load
Counter
Figure 28.28 Example of the Operation of the Drum Speed Error Detection
Rev. 2.0, 11/00, page 690 of 1037
Specified speed value
Preset value
(Selection of the Rising Edge of DFG)
Preset period
(2 counts)
–value+value
Latch data 0
(no error)