Renesas Hitachi H8S/2194 Series Hardware Manual page 510

Initialization
Start reception
Set MPIE bit in SCR1 to 1
Read ORER and FER flags in SSR1
FER∨ORER=1
Read RDRF flag in SSR1
No
RDRF=1
Read receive data in RDR1
No
This station's ID?
Read ORER and FER flags in SSR1
FER∨ORER=1
Read RDRF flag in SSR1
RDRF=1
Read receive data in RDR1
No
All data received?
Clear RE bit in SCR1 to 0
< End >
Figure 23.12 Sample Multiprocessor Serial Reception Flowchart (1)
[1]
[2]
Yes
No
[3]
Yes
Yes
Yes
No
No
Yes
Error handling
Yes
(Continued on
next page)
SCI1 initialization:
[1]
The SI1 pin is automatically designated as
the receive data input pin.
ID reception cycle:
[2]
Set the MPIE bit in SCR1 to 1.
[3] SCI1 status check, ID reception and
comparison:
Read SSR1 and check that the RDRF flag
is set to 1, then read the receive data in
RDR1 and compare it with this station's ID.
If the data is not this station's ID, set the
MPIE bit to 1 again, and clear the RDRF
flag to 0.
If the data is this station's ID, clear the
RDRF flag to 0.
SCI1 status check and data reception:
[4]
Read SSR1 and check that the RDRF flag
is set to 1, then read the data in RDR1.
Receive error handling and break
[5]
detectioon:
If a receive error occurs, read the ORER
and FER flags in SSR1 to identify the error.
After performing the appropriate error
handling, ensure that the ORER and FER
flags are both cleared to 0.
Reception cannot be resumed if either of
these flags is set to 1.
In the case of a framing error, a break can
be detected by reading the SI1 in value.
[4]
[5]
Rev. 2.0, 11/00, page 483 of 1037