Renesas Hitachi H8S/2194 Series Hardware Manual page 959

H'D061: HSW Mode Register 2 HSM2: HSW Timing Generator
7
Bit :
FRT FGR20FF
0
Initial value :
R/W
R/W :
FRG2 clear stop bit
0 16-bit counter clear by DFG reference register 2 is enabled
1 16-bit counter clear by DFG reference register 2 is disabled
Free-run bit
0 5-bit DFG counter and 16-bit timer
1 16-bit FRC
Rev. 2.0, 11/00, page 932 of 1037
6 5 4
LOP EDG
0 0 0
R/W R/W R/W
DFG edge select bit
0 Calculated by DFG rising edge
1 Calculated by DFG falling edge
Mode select bit
0 Signal mode
1 Loop mode
3 2
ISEL1 SOFG
0 0
R/W R/W
Output FIFO group flag
0
1
FIFO output group select bit
0 20-level output by FIFO1 and FIFO2
1 10-level output by FIFO1 only
Interrupt select bit
0 Interrupt request is generated by rising of FIFO STRIG signal
1 Interrupt request is generated by FIFO match signal
1 0
OFG VFF/NFF
0 0
R R/W
VideoFF/NarrowFF output switchover bit
0 VideoFF output
1 NarrowFF output
Outputting pattern by FIFO1
Outputting pattern by FIFO2