Renesas Hitachi H8S/2194 Series Hardware Manual page 102

Bit 6
LSON Description
• When a SLEEP instruction is executed in high-speed mode or medium-speed
0
mode, transition is made to sleep mode, standby mode, or watch mode
• When a SLEEP instruction is executed in subactive mode, a transition is made
to watch mode, or directly to high-speed mode
• After watch mode is cleared, a transition is made to high-speed mode
• When a SLEEP instruction is executed in high-speed mode a transition is made
1
to watch mode, subactive mode, sleep mode or standby mode
• When a SLEEP instruction is executed in subactive mode, a transition is made
to subsleep mode or watch mode
• After watch mode is cleared, a transition is made to subactive mode
Bit 5: Noise Elimination Sampling Frequency Select (NESEL)
Selects the frequency at which the subclock (φw) generated by the subclock pulse generator is
sampled with the clock (φ) generated by the system clock oscillator. When φ = 5 MHz or higher,
clear this bit to 0.
Bit 5
NESEL Description
Sampling at φ divided by 16
0
Sampling at φ divided by 4
1
Bits 4 to 2: Reserved.
These bits cannot be modified and are always read as 0.
Bit 1, 0: Subactive mode clock select 1, 0 (SA1, SA0)
These bits select the CPU operating clock in the subactive mode. These bits cannot be modified
in the subactive mode.
Bit 1 Bit 0
SA1 SA0
0 0
0 1
1
*
Note: Don't care
*
Description
Operating clock of CPU is φw/8
Operating clock of CPU is φw/4
Operating clock of CPU is φw/2
(Initial value)
(Initial value)
Rev. 2.0, 11/00, page 75 of 1037