Timer Counter A (Tca); Module Stop Control Register (Mstpcr) - Renesas Hitachi H8S/2194 Series Hardware Manual

12.2.2

Timer Counter A (TCA)

Bit :
TCA7
Initial value :
R/W :
The timer counter A (TCA) is an 8-bit up-counter which counts up on inputs from the internal
clock. The inputting clock can be selected by TMA3 to TMA0 bits of the TMA
When the TCA overflows, the TMAOV bit of the TMA is set to 1.
The TCA can be cleared by setting the TMA3 and TMA2 bits of the TMA to 11.
The TCA is always readable. When reset, the TCA will be initialized into H'00.
12.2.3

Module Stop Control Register (MSTPCR)

7
Bit :
MSTP15
Initial value :
1
R/W :
R/W
The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode.
When the MSTP15 bit is set to 1, the Timer A stops its operation at the ending point of the bus
cycle to shift to the module stop mode. For more information, see section 4.5, Module Stop
Mode. When reset, the MSTPCR will be initialized into H'FFFF.
Bit 7: Module Stop (MSTP15)
This bit works to designate the module stop mode for the Timer A.
MSTPCRH
Bit 7
MSTP15 Description
0 Cancels the module stop mode of the Timer A
1 Sets the module stop mode of the Timer A
7 6 5
TCA6 TCA5
0 0 0
R R R
MSTPCRH
6 5 4 3
MSTP14 MSTP13 MSTP12 MSTP11 MSTP10
1 1 1 1
R/W R/W R/W R/W R/W
4 3
TCA4 TCA3
0 0
R R
2 1 0 7 6
MSTP9 MSTP8 MSTP7 MSTP6
1 1 1 1 1
R/W R/W R/W R/W
2 1
TCA2 TCA1
0 0
R R
MSTPCRL
5 4 3 2
MSTP5 MSTP4 MSTP3 MSTP2
1 1 1 1
R/W R/W R/W R/W
Rev. 2.0, 11/00, page 293 of 1037
0
TCA0
0
R
1 0
MSTP1 MSTP0
1 1
R/W R/W
(Initial value)