Asynchronous External Reset Pin; External Power-On Reset; Internal Low Voltage Detector (Lvd) Reset; Figure 12. Reset Sequence Phases - STMicroelectronics ST72361 Auto Series Manual

Supply, reset and clock management
The reset vector fetch phase duration is two clock cycles.

Figure 12. RESET sequence phases

5.5.2

Asynchronous external RESET pin

The RESET pin is both an input and an open-drain output with integrated R
resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled low by external circuitry to reset the device. See
characteristics
A reset signal originating from an external source must have a duration of at least t
in order to be recognized (see
MCU can enter reset state even in HALT mode.

Figure 13. Reset block diagram

RESET
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In
a noisy environment, it is recommended to follow the guidelines mentioned in the electrical
characteristics section.
5.5.3

External power-on reset

If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must
ensure by means of an external reset circuit that the reset signal is held low until V
the minimum level specified for the selected f
A proper reset signal for a slow rising V
RC network connected to the RESET pin.
5.5.4

Internal low voltage detector (LVD) reset

Two different reset sequences caused by the internal LVD circuitry can be distinguished:
●
Power-on reset
●
Voltage drop reset
42/279
Active Phase
for more details.
Figure
V
DD
R
ON
Doc ID 12468 Rev 3
RESET
INTERNAL RESET
256 or 4096 CLOCK CYCLES
14). This detection is asynchronous and therefore the
Filter
PULSE
GENERATOR
frequency.
OSC
supply can generally be provided by an external
DD
ST72361xx-Auto
FETCH
VECTOR
weak pull-up
ON
Chapter 20: Electrical
INTERNAL
RESET
WATCHDOG RESET
LVD RESET
h(RSTL)in
is over
DD