Table 49. Clock Source Stabilization Times - STMicroelectronics STM32WLEx Reference Manual

RM0461
The LSI RC can be switched on and off using the LSION bit in the
register (RCC_CSR).
The LSIRDY flag in the
oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware.
An interrupt can be generated if enabled in the
(RCC_CIER).
6.2.7 Clock source stabilization time
The different clock sources require a stabilization time, during which no clock is forwarded to
the system (see the table below).
Clock source
6.2.8 System clock (SYSCLK) selection
The following clock sources can be used to drive the system clock (SYSCLK):
•
MSI oscillator
•
HSI16 oscillator
•
HSE32 oscillator (either 32 MHz or divided by 2 for 16 MHz)
•
PLLRCLK
The system clock maximum frequency in range 1 is 48 MHz. After a system reset, the MSI
oscillator, at 4 MHz, is selected as system clock. When a clock source is used directly or
through the PLL as a system clock, it is not possible to stop it.
A switch from one clock source to another occurs only if the target clock source is ready
(clock stable after startup delay or PLL locked). If a clock source that is not yet ready is
selected, the switch occurs when the clock source becomes ready. Status bits in the
internal clock sources calibration register (RCC_ICSCR)
ready and which clock is currently used as a system clock.
When waking up from Standby mode, the MSI at 4 MHz is selected as system clock.
In range 2, the system clock must not exceed 16 MHz.
RCC control/status register (RCC_CSR)

Table 49. Clock source stabilization times

MSI Refer to the device datasheet.
HSI Refer to the device datasheet.
HSE Refer to the device datasheet.
2 cycles (~85 μs LSIPRE = 0)
LSI
2 cycles (~2 ms LSIPRE = 1)
LSE 4096 cycles (125 ms)
RM0461 Rev 5
Reset and clock control (RCC)
RCC control/status
indicates if the LSI
RCC clock interrupt enable register
Stabilization time
indicate which clock(s) is (are)
RCC
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