Lsi Clock; Clock Source Stabilization Time; System Clock (Sysclk) Selection; Table 57. Clock Source Stabilization Times - STMicroelectronics STM32WL5 Series Reference Manual

RM0453
External source (LSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to
1 MHz. This mode is selected by setting the LSEBYP and LSEON bits in the
domain control register
with ~50 % duty cycle must drive the OSC32_IN pin while the OSC32_OUT pin can be used
as GPIO (see
7.2.6

LSI clock

The LSI RC acts as a low-power clock source that can be kept running in Stop and Standby
modes for the independent watchdog (IWDG) and RTC. The clock frequency is ~32 kHz or
can be divided by 128 (~250 Hz) using LSIPRE. For more details, refer to the electrical
characteristics section of the datasheets.
The LSI RC can be switched on and off using the LSION bit in the
register (RCC_CSR).
The LSIRDY flag in the
oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware.
An interrupt can be generated if enabled in the
(RCC_CIER).
7.2.7

Clock source stabilization time

The different clock sources require a stabilization time, during which no clock is forwarded to
the system (see the table below).
Clock source
7.2.8

System clock (SYSCLK) selection

The following clock sources can be used to drive the system clock (SYSCLK):
• MSI oscillator
•
HSI16 oscillator
• HSE32 oscillator (either 32 MHz or divided by 2 for 16 MHz)
•
PLLRCLK
The system clock maximum frequency in range 1 is 48 MHz. After a system reset, the MSI
oscillator, at 4 MHz, is selected as system clock. When a clock source is used directly or
through the PLL as a system clock, it is not possible to stop it.
(RCC_BDCR). The external clock signal (square, sinus or triangle)
Figure 30: LSE clock
RCC control/status register (RCC_CSR)

Table 57. Clock source stabilization times

MSI Refer to the device datasheet.
HSI Refer to the device datasheet.
HSE Refer to the device datasheet.
2 cycles (~85 μs LSIPRE = 0)
LSI
2 cycles (~2 ms LSIPRE = 1)
LSE 4096 cycles (125 ms)
RM0453 Rev 5
sources).
RCC clock interrupt enable register
Stabilization time
Reset and clock control (RCC)
RCC backup
RCC control/status
indicates if the LSI
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